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preliminary data sheet, v0.9, april 2008 PMA7110 rf transmitter ic with embedded 8051 microcontroller, lf 125khz ask receiver and fsk/ask 315/434/868/915 mhz transmitter sense & control targetdatasheet.book page 1 monday, april 28, 2008 11:16 am
edition 2008-04-28 published by infineon technologies ag, am campeon 1-12 85579 neubiberg, germany ? infineon technologies ag 2008-04-28. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or the infineon technologies companies and our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. targetdatasheet.book page 2 monday, april 28, 2008 11:16 am
preliminary data sheet, v0.9, april 2008 PMA7110 rf transmitter ic with embedded 8051 microcontroller, lf 125khz ask receiver and fsk/ask 315/434/868/915 mhz transmitter sense & control targetdatasheet.book page 3 monday, april 28, 2008 11:16 am
PMA7110 preliminary data sheet 4 v0.9, 2008-04-28 PMA7110 revision history:2008-04-28 v0.9 page 129 update typical value of transmit current consumption page 132 update rf characterization for d9 ~ d17 page 128 , page 141 update flash code/data memory progra m temeprature and erase cycle: b4, o1, o2, o6 ~ o8. we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: sensors@infineon.com targetdatasheet.book page 4 monday, april 28, 2008 11:16 am
preliminary data sheet 5 v0.9, 2008-04-28 PMA7110 targetdatasheet.book page 5 monday, april 28, 2008 11:16 am
PMA7110 preliminary data sheet 6 v0.9, 2008-04-28 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3 operating modes and states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.1 operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.2 state description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2.1 init state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2.2 run state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.2.3 idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.2.4 power down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.2.5 thermal shutdown state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.2.6 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.2.7 status of PMA7110 blocks in different states . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.1 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.2 vmin detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.3 flash memory checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.4 adc measurement overflow & underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.5 tmax detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5.1 sensor interfaces and data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5.1.1 sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5.1.2 two differential high sensitive interfaces to external sensors . . . . . . . . . . . . 43 2.5.1.3 interface to other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.1.4 reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.1.5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5.1.6 battery voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5.2 memory organization and special function registers (sfr) . . . . . . . . . . . . . . 47 2.5.2.1 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.5.2.2 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.5.2.3 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.2.4 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.3 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.5.4 system configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.5.5 general purpose registers (gpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.5.6 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.5.6.1 wakeup logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.5.6.2 interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 targetdatasheet.book page 6 monday, april 28, 2008 11:16 am
preliminary data sheet 7 v0.9, 2008-04-28 PMA7110 2.5.6.3 interval timer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.5.7 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.5.7.1 2 khz rc lp oscillator (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.5.7.2 12 mhz rc hf oscillator (high frequency) . . . . . . . . . . . . . . . . . . . . . . . . 71 2.5.7.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.5.8 interrupt sources on the . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.5.9 rf 315/434/868/915 mhz fsk/ask transmitter . . . . . . . . . . . . . . . . . . . . . . . 78 2.5.9.1 phase locked loop pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.5.9.2 power amplifier pa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.5.9.3 ask modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.5.9.4 voltage controlled oscillator (vco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.5.9.5 manchester/biphase encoder with bit rate generator . . . . . . . . . . . . . . . . . . 81 2.5.10 lf receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.5.11 16bit crc (cyclic redundancy check) genera tor/checker . . . . . . . . . . . . . . . 86 2.5.12 pseudo random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.5.13 timer unit (timer 0, timer 1, timer 2, timer 3) . . . . . . . . . . . . . . . . . . . . . . . 90 2.5.13.1 basic timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.5.13.2 general operation description timer 0 and timer 1 . . . . . . . . . . . . . . . . . . . 93 2.5.13.3 timer modes for timer 2 and timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.5.14 general purpose input/output (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.5.14.1 peripheral port basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.5.14.2 spike suppression on input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.5.14.3 external wakeup on pp1-pp4 and pp6-pp9 . . . . . . . . . . . . . . . . . . . . . . . . 109 2.5.14.4 alternative port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.5.15 i2c- interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.5.15.1 slave mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.5.15.2 general call sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.5.15.3 master mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.5.16 serial peripheral interface spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.5.17 programming mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.5.17.1 flash write line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.5.17.2 flash erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.5.17.3 flash check erase status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.5.17.4 flash read line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 2.5.17.5 flash set lockbyte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 2.5.17.6 flash set lockbyte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 2.5.17.7 read status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.5.18 debug mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.5.18.1 debug special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.5.18.2 debugging facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.5.18.3 debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 targetdatasheet.book page 7 monday, april 28, 2008 11:16 am
PMA7110 preliminary data sheet 8 v0.9, 2008-04-28 3.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.1.3 product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.2 reference sfr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 3.3 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 targetdatasheet.book page 8 monday, april 28, 2008 11:16 am
preliminary data sheet 9 v0.9, 2008-04-28 PMA7110 product description 1 product description 1.1 overview the PMA7110 is a low power wireless fsk/ask transmitter with embedded microcon- troller, which offers a single chip solution for various industrial, consumer and automo- tive applications in frequency bands 315/434/868/915 mhz. with its highly integrated mixed signal peripherals, PMA7110 requires only few external components. the oper- ating voltage range is 1.9 - 3.6 v. the PMA7110 contains ? 8051 based microcontroller ? advanced power control system to minimize power consumption ? rf transmitter ?lf receiver ? multifunctional interface for external sensors and embedded temperature and battery voltage sensor measurement via embedded temperature and voltage sensor, reading signal from analog inputs (e.g. from external analog sensor) are performed under software control, so that the microcontroller can format and prepare this data for the rf transmission. an intelligent power control system enables the build of ultra low power applications by using powersaving modes. the integrated microcontroller is instruction set compatible to the standard 8051 processor. it is equipped with various peripherals (e.g. a hardware manchester/biphase encoder/decoder and crc generator/checker) enabling an easy implementation of customer-specific applications. the low power consumption fsk/ask transmitter for 315/434/868/915 mhz frequency bands contains a fully integrated vco, a pll synthesizer, an ask/ fsk modulator and an efficient power amplifier. fine tuning of the center frequency can be done by an on- chip capacitor bank. to store the microcontroller application program code and its unique id-number, an on- chip flash memory is integrated. additional rom storage is provided for the rom library functions covering standard tasks required by various applications. targetdatasheet.book page 9 monday, april 28, 2008 11:16 am
PMA7110 product description preliminary data sheet 10 v0.9, 2008-04-28 1.2 features ? supply voltage range from 1.9 v up to 3.6 v ? operating temperature range -40 to +85 c ? low supply current ? temperature sensor ? battery voltage measurement ? integrated rf- transmitter for ism band 315/434/868/915 mhz ? selectable transmit power 5/8/10 dbm into 50 ohm load ? transmit data rates up to 32kbit/s or 64kchips/s in manchester code ? fsk/ask modulation capability ? frequency deviation up to 100 khz in fsk mode ? fully integrated vco and pll synthesizer ? crystal oscillator tuning on chip ? lf receiver with input signal amplitude of min. 0.25 mvpp ? lf receiver data rate from 2000 bit up to 4000 bit (manchester/biphase coded) ? 8051 instruction set compatible microcontroller (cycle-optimized) ? 6 kbyte flash code and 2x128 bytes flash data memory (for user-application like eeprom emulation) ? 12 kbyte rom (for rom library functions) ? 256 bytes ram (128 bytes configurable to keep content in power down mode), 16 bytes xdata memory (supplied in powerdown) ?i 2 c bus interface ? spi bus interface ? 10 free programmable bidirectional gpio pins with on chip pull-up/down resistors ? 4 independent 16 bit timers ? 10bit adc with 3 pair differential channels (e.g. as io for external sensors) ? wakeup from power down state using the interval timer, the lf receiver or external wakeup sources connected via a gpio ? manchester/biphase encoder and decoder ? hardware crc generator ? pseudo random number generator ? watchdog timer ? on chip debugging via i 2 c interface note:in PMA7110 the thermal shout down function is not used. 1.3 applications ? remote control systems for industrial and consumer applications ? security- and alarm-systems ? home automation systems ? automatic meter reading ? active tagging targetdatasheet.book page 10 monday, april 28, 2008 11:16 am
preliminary data sheet 11 v0.9, 2008-04-28 PMA7110 functional description 2 functional description 2.1 pin description figure 1 pin-out of PMA7110 in tssop38 package v2n (sens) vm2 (sens) v2p (sens) rd (sens) gndc vdda vddd vreg lf xlf amux2 amux1 xgnd xtal/sclk xtalcap tme mse pp9/ext_int0/wu 7 pp8/wu6 PMA7110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 vdd (sens) v1n (sens) vm1 (sens) v1p (sens) gndb gnda vbat pgnd pa gnd pp2/wu1/txdataout pp1/wu0/i2c_sda/opmode2 pp0/i2c_scl/opmode1 pp3/spi_cs/wu2 pp4/wu3/spi_miso pp5/spi_mosi pp6/wu4/spi_clk xreset pp7/ext_int1/wu5 targetdatasheet.book page 11 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 12 v0.9, 2008-04-28 table 1 pin description pin name type description comments 1 vdd(sens.) supply sensor positive supply same voltage as chip analog supply 2 v1n(sens.) analog channel1, negative sensor input output of wheatstone bridge sensor 3 vm1(sens.) supply sensor negativ e supply same voltage as chip gnd 4 v1p(sens.) analog channel1, positiv e sensor input output of wheatstone bridge sensor 5 gndb supply ground 6 gnda supply ground 7 vbat supply battery supply voltage 8 pgnd supply rf transmitter ground 9 pa analog rf transmitter output 10 gnd analog ground 11 pp2/wu1/ txdataout digital gpio, external wakeup source, serial output of manchester/biphase encoded data internal pullup/pulldown switchable 12 pp1/wu0/ i2c_sda/ opmode2 digital gpio, external wakeup source, i2c bus interface data, select operation mode internal pullup/pulldown switchable 13 pp0/ i2c_scl/ opmode1 digital gpio, i2c bus interface clock, select operation mode internal pullup/pulldown switchable 14 pp3/spi_cs/ wu2 digital gpio, spi bus interface chip select, external wakeup source internal pullup/pulldown switchable 15 pp4/wu3 /spi_miso digital gpio, spi bus interface master in slave out, external wakeup source internal pullup/pulldown switchable 16 pp5/ spi_mosi digital gpio, spi bus interface master out slave in internal pullup/pulldown switchable 17 pp6/wu4 /spi_clk digital gpio, spi bus interface clock, external wakeup source internal pullup/pulldown switchable targetdatasheet.book page 12 monday, april 28, 2008 11:16 am
preliminary data sheet 13 v0.9, 2008-04-28 PMA7110 functional description 18 xreset digital external reset low active 19 pp7/wu5 /ext_int1 digital gpio, external wakeup source internal pullup/pulldown switchable 20 pp8/wu6 digital gpio, external wakeup source internal pullup/pulldown switchable 21 pp9/wu7 /ext_int1 digital gpio, external wakeup source, external interrupt source internal pullup/pulldown switchable 22 mse digital mode select enable high active, set to gnd in normal mode 23 tme digital test mode enable high active, set to gnd in normal mode 24 xtalcap analog crystal oscillator load capacitance 25 xtal/sclk analog crystal oscillator input, external reference clock 26 xgnd supply crystal oscillator ground 27 amux1 analog additional differential adc standard input1 for external sensor connect to gnd if not use 28 amux2 analog additional differential adc standard input2 for external sensor connect to gnd if not use 29 xlf analog differential lf receiver input2 30 lf analog differential lf receiver input1 31 vreg supply internal voltage regulator output connect to decoupling capacitor (c bcap =100nf) 32 vddd supply digital supply 33 vdda supply analog supply 34 gndc supply ground 35 rd(sens.) analog use only by having diagnostic resistor on sensor bridge, otherwise none connection table 1 pin description pin name type description comments targetdatasheet.book page 13 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 14 v0.9, 2008-04-28 36 v2p(sens.) analog channel2, positiv e sensor input output of wheatstone bridge sensor 37 vm2(sens.) supply sensor negative supply same voltage as chip gnd 38 v2n(sens.) analog channel2, negative sensor input output of wheatstone bridge sensor table 1 pin description pin name type description comments targetdatasheet.book page 14 monday, april 28, 2008 11:16 am
preliminary data sheet 15 v0.9, 2008-04-28 PMA7110 functional description table 2 pin i/o equivalent schematics pin no. pad name equivalent i/o schematic function 1 vdd (sens.) sensor positive supply 2 v1n (sens.) channel 1 negative signal vbat vreg vo lta g e regulator gnd gnd vdd (sens) gnd sw itch vdd a 500 v1n 2k targetdatasheet.book page 15 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 16 v0.9, 2008-04-28 3 vm1 (sens.) channel 1 negative supply 4 v1p (sens.) channel 1 positive signal 5 gndb ground pin no. pad name equivalent i/o schematic function vdd a gnd vm1 vdd a 500 v1p 2k gndb xgnd pgnd targetdatasheet.book page 16 monday, april 28, 2008 11:16 am
preliminary data sheet 17 v0.9, 2008-04-28 PMA7110 functional description 6 gnda 7 vbat power supply voltage regulators 8pgnd double bond power amplifier ground pin no. pad name equivalent i/o schematic function gnda xgnd pgnd vbat vreg vo lta ge regulator gnd xgnd pgnd targetdatasheet.book page 17 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 18 v0.9, 2008-04-28 9 pa power amplifier output stage 10 gnd 11 pp2/wu1 /txdataout gpio port wu1 serial output of manchester/biphase encoded data pin no. pad name equivalent i/o schematic function pa pgnd pgnd 10 program7v 100 data tristate 500 1.8 ... 3.6v pp2 vba t gnd core amux3 gnd 2k 0 1 7 vba t pullup pulldo wn tristate 250k pps2 ppo2 vba t gnd vba t analog signals ppd2 2k dmux2 core dmux1 ppo2 ppo2 tmd1_xclkdiv tmd1_wucde t tmd1_lfraw tmd1_clk_cpu tmd1_pll_fc txdata rftxpen ppi2 combinatorial log ic amu x3 tg targetdatasheet.book page 18 monday, april 28, 2008 11:16 am
preliminary data sheet 19 v0.9, 2008-04-28 PMA7110 functional description 12 pp1/ wu0/i2c_sda /opmode2 gpio port wu0 i2c_sda opmode2 13 pp0/i2c_scl /opmode1 gpio port i2c_scl opmode1 pin no. pad name equivalent i/o schematic function ppi1 ppd1 data tristate 500 data pp1 vbat gnd vbat pps1 pullup pulldown tristate 50k vbat gnd combinatori al logic combinatorial logic ppo1 i2cd i2cen ppi0 ppd0 data tristate 500 data pp0 vbat gnd vbat pps0 pullup pulldown tr istate 50k vbat gnd combinatori al logic combi natorial logic ppo0 i2cclk i2cen targetdatasheet.book page 19 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 20 v0.9, 2008-04-28 14 pp3/spi_cs /wu2 gpio port wu2 spi_cs 15 pp4/wu3 /spi_miso gpio port wu3 spi_miso 16 pp5/spi_mosi gpio port spi_mosi pin no. pad name equivalent i/o schematic function ppi3 ppd3 data tristate 500 data pp3 vbat gnd 2k dmux4 core dmux2 pps3 pullup pulldown tristate 250k vbat gnd ppo3 ppo3 co mb i n at o ri al logic combi natorial logi c ppo3 dmux3 tmd2_wucdet tmd2_lfraw tmd2_bitbounddet tmd2_decerr ppi4 ppd4 data tristate 500 data pp4 vbat gnd vbat pps4 pullup pulldown tristate 50k vbat gnd c om binat ori al logi c co m bi nat or ial logic ppo4 spi_miso spien ppi5 ppd5 data tristate 500 data pp5 vbat gnd vbat pps5 pullup pulldown tristate 50k vbat gnd c om bi nat ori al logi c co m bi n at or i al logi c ppo5 spi_mosi spien targetdatasheet.book page 20 monday, april 28, 2008 11:16 am
preliminary data sheet 21 v0.9, 2008-04-28 PMA7110 functional description 17 pp6/wu4 /spi_clk gpio port wu4 spi_clk 18 xreset reset input 19 pp7/wu5 /ext_int1 gpio port wu5 ext_int1 pin no. pad name equivalent i/o schematic function ppi6 data tristate 500 data pp6 vbat gnd 2k dmux5 core dmux3 pps6 pullup pulldown tristate 50k vbat gnd ppo6 ppo6 combinatori al logic ppo6 tmd3_syncmatch ppd6 spi_clk spien com binatorial logic 50k 500 xreset rese t vbat ppi7 ppd7 data tristate 500 data pp7 vbat gnd 2k core dmux4 pps7 pullup pulldown tristate 50k vbat gnd ppo7 ppo7 co mb i n a t o r i al logic com bi natorial logi c ppo7 dmux6 tmd4_chipvalid targetdatasheet.book page 21 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 22 v0.9, 2008-04-28 20 pp8/wu6 gpio port wu6 21 pp9/wu7 /ext_int0 gpio port wu7 ext_int0 22 mse mode select enable pin no. pad name equivalent i/o schematic function ppi8 ppd8 data tristate 500 data pp8 vbat gnd 2k core dmux5 pps8 pullup pulldown tristate 250k vbat gnd ppo8 ppo8 co mbi n at o ri al logic com binatorial logi c hirc clock tmd6_tr_so tmd5_flash_dig0 ppi9 ppd9 data tristate 500 data pp9 vbat gnd 2k core dmux6 pps9 pullup pulldown tristate 250k vbat gnd ppo9 ppo9 combinatori al logic combi natorial logi c lorc clock tmd5_chip tmd6_flash_dig1 250k 500 mse mse_i vbat targetdatasheet.book page 22 monday, april 28, 2008 11:16 am
preliminary data sheet 23 v0.9, 2008-04-28 PMA7110 functional description 23 tme test mode enable 24 xtalcap crystal oscillator output 25 xtal/sclk crystal oscillator input sclk pin no. pad name equivalent i/o schematic function 250k 500 tme tme_i vbat xtalcap xgn d xgn d 10 vddd xgn d 500 xgnd xtal 0.9vdc bypass targetdatasheet.book page 23 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 24 v0.9, 2008-04-28 26 xgnd crystal oscillator ground 27 amux1 additional differential adc standard input1 for external sensor , analog testsignal port 28 amux2 additional differential adc standard input2 for external sensor, analog testsignal port 29 xlf low frequency input pin no. pad name equivalent i/o schematic function gnd xgnd pgnd vdda gnd 500 gnd 2k 0 1 7 amux1 core vdd a gnd 500 gnd 2k 0 1 7 amux2 core xlf gnd 50 15k xlf_i targetdatasheet.book page 24 monday, april 28, 2008 11:16 am
preliminary data sheet 25 v0.9, 2008-04-28 PMA7110 functional description 30 lf low frequency input 31 vreg regulated power supply 32 vddd digital supply 33 vdda analog supply pin no. pad name equivalent i/o schematic function lf gnd 50 15k lf_i vbat vreg voltage regulator gnd gnd 1 .6 ...2.5v vddd gnd digital core vdda gnd an a lo g co re targetdatasheet.book page 25 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 26 v0.9, 2008-04-28 34 gndc ground 35 rd (sens.) connect to diagnostic resister on sensor bridge, otherwise no connection 36 v2p (sens.) channel 2 positve signal pin no. pad name equivalent i/o schematic function gndc xgnd pgnd vdda 500 rd 2k 100k vdda 500 v2p 2k targetdatasheet.book page 26 monday, april 28, 2008 11:16 am
preliminary data sheet 27 v0.9, 2008-04-28 PMA7110 functional description 37 vm2 (sens.) channel 2 negative supply 38 v2n (sens.) channel 2 negative signal pin no. pad name equivalent i/o schematic function vd d a vm2 vdda 500 v2n 2k targetdatasheet.book page 27 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 28 v0.9, 2008-04-28 2.2 functional block diagram figure 2 PMA7110 block diagram rf transmitter manchester 101 phase codes adc input multiplexer t b adc reference voltage & offset dac adc state machine microcontroller with 8051 core bandgap and ptat system controller 6 kb flash 12 kb rom 256 b ram crc generator general purpose input/output (gpio, i2c, spi, wu?) brownout detector vmin and tmax detector special function registers (sfr) lf receiver 2khz rc lp oscillator 12mhz rc hf oscillator watch dog timer timer interval timer timer calibration clo c k co ntro ll er reset wake up power mgm power amp crystal oscillator fsk modulator ask modulator rf-pll 125khz receiver carrier detector digital receiver 6 kb flash pa pgnd xgnd xtalcap xtal lf xlf pp0 pp1 pp2 pp9 .. . .. . diff. high sensitive input1 diff. high sensitive input2 xreset diff. standard input interrupt controller test controller mse tme v1p v1n v2p v2n amux1 amux2 gn d vba t vreg voltage regulators low power v-reg low dropout v-reg prng vdda vd dd targetdatasheet.book page 28 monday, april 28, 2008 11:16 am
preliminary data sheet 29 v0.9, 2008-04-28 PMA7110 functional description 2.3 operating modes and states the PMA7110 can be operated in four different operating modes. ?normalmode ?programmingmode ? debug mode ? (internal production test mode) 2.3.1 operating mode selection figure 3 operating mode selection of the PMA7110 after reset the mode select is entered after the system reset expires and scan test mode is not selected. the levels on the the i/o pins pp0 and pp1 are latched by the system controller and read by the operating system to determine the mode of operation of the device according to table 3 "operating mode selection after reset" on page 30 . therefore also the status of mse and lockbyte ii from the flash are checked. the mode select programming mode functional test mode mse = 1 pp0=0 pp1=0 mse = 1 pp0=1 pp1=0 lockbyte ii not set mse = 1 pp0=0 pp1=1 lockbyte ii not set s f r c f g 0 . 3 = 1 l o c k b y t e i i n o t s e t sfr cfg0. 3=0 scan test mode tme = 1 por, xreset software reset brown-out event system reset ** *note: if lockbyte i and/or ii is set, only a reduced test command set is available tme = 0 mse = 0 or mse = 1 pp0=1|1|0 pp1=1|0|1 lockbyte ii set or mse = 1 pp0=1 pp1=1 lockbyte ii not set test mode 0 * debug mode normal mode **note: whenever tme is set to high the current operation mode is left and scan test mode is entered, regardless if there was a reset event or not! targetdatasheet.book page 29 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 30 v0.9, 2008-04-28 mse, pp0 and pp1 levels must not change after reset release during the whole t mode period (see figure 5 "power on reset - operating mode selection" on page 32 ). table 3 operating mode selection after reset tme mse lock byte ii pp0 pp1 operating mode devicecontrol hardware restrictions 1 3.) x x x x scan external test machine n.a. 0 0 x x x normal cpu executing from 4000h flash write disabled 2) 0 1 x 0 0 test test mode handler none 01not set 0 1 programming program mode handler none 0 1 set 0 1 normal cpu executing from 4000h flash write disabled 2.) 01not set 1 0 debug debug mode handler flash write disabled 2.) 0 1 set 1 0 normal cpu executing from 4000h flash write disabled 2.) 0 1 x 1 1 normal cpu executing from 4000h flash write disabled 2.) 1.) flash protection is done by hardware. in these modes setting the sfr bits fcs.3 [prog] and fcs.2 [erase] is not possible. 2.) flash programming and erasing is only possible via rom library functions. 3.) whenever tme is set to high the current mode is left immediately and scan test mode is entered, regardless if there is a reset or not. targetdatasheet.book page 30 monday, april 28, 2008 11:16 am
preliminary data sheet 31 v0.9, 2008-04-28 PMA7110 functional description . figure 4 normal mode - state transistion diagram for low power consumption and safety reasons the PMA7110 supports different operating states - run state, idle state and power down mode and thermal shutdown state. the device operation in these states is described below. transitions between these states are either application software controlled or managed automatically by the system controller. - pdwn: powerdown (cpu & peripherrals stopped) - idle: cpu clock stopped, peripherals are still running pdwn run wd pe te wu wu mse = 0 or mse = 1 pp0=1|1|0 pp1=1|0|1 lockbyte ii set or mse = 1 pp0=1 pp1=1 lockbyte ii not set mode select states tsht - thermal shutdown run - run application pdwn - powerdown idle - cpu clock stopped idle transitions wu - wakeup pe - powerdown enable te - thermal shutdown enabl e wd - watchdog iflg - idle flag rs - resume irq - interrupt request reti- return from interrupt init rs iflg irq reti idle tsht wd targetdatasheet.book page 31 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 32 v0.9, 2008-04-28 figure 5 power on reset - operating mode selection during the time t mode , the levels of pp0, pp1 and mse are read, and being determined the operation mode of the device according to table 3 "operating mode selection after reset" on page 30 . the levels on these pins must be stable during the whole t mode period. the PMA7110's power on reset circuit is activated if vreg rises above v por . the internal blocks are held in reset state until vreg has risen above v thr . when this reset state is released, a further time of t mode is needed for reading the levels on pp0, pp1 and mse. after t mode has elapsed, the device starts operation in the selected mode. note: see ?power on reset? on page 138 for details on power on reset characteristics. 2.3.2 state description 2.3.2.1 init state this is a transient state which is entered when the settings of pp0, pp1, mse, tse and the lockbyte ii lead to normal mode (please refer to table 3 "operating mode selection after reset" on page 30 ). in this state, the sfrs which are not located in the system controller get reset and the rom routines initializes the system to its default vreg v por v thr reset (internal) t por pp0, pp1 t mode targetdatasheet.book page 32 monday, april 28, 2008 11:16 am
preliminary data sheet 33 v0.9, 2008-04-28 PMA7110 functional description values. then the application program in flash is started at 4000h and the device enters run state. 2.3.2.2 run state in run state the cpu8051 executes programs stored in rom or flash memory. peripherals are on or off according to the application program. the watchdog (wd) is active and automatically cleared when entering run state on a wakeup event. the cpu clock frequency is selectable by software. all wakeup events are ignored in run state but the corresponding flags get set and can be read and cleared. 2.3.2.3 idle state in idle state, the cpu8051 clock is disabled but peripherals (timers, adc, rf-tx, spi, i 2 c interface and manchester/biphase coder) continues normal operation. if a resume condition occurs the run state is reentered immediatelly. the watchdog (wd) is active and reset automatically when entering idle state. all wakeups are ignored in idle state but the corresponding flags are set if a wakeup occurs and can be evaluated once the device returns to the run state. in case of a peripheral requests, an interrupt or an external interrupt occurs the idle state is left for run state, the interrupt service routine is executed and on the next reti (return from interrupt) instruction the idle state is re-entered in case no resume event has occured in between. resume events: the resume source can be identified by reading ref. resume events may occur on following events: ? rf transmitter buffer empty. ? rf transmission finished. ? lf receiver buffer full. ? timer 2 underflow. ? a/d conversion finished. ? rc-lp-oscillator calibration finished. ? clock change from rc-hf-oscillator to crystal-oscillator finished. interrupt requests: interrupts during idle state may be requested by embedded peripherals or external events. ? external (pin) interrupt 0/1 ? timer 0/1/2/3 targetdatasheet.book page 33 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 34 v0.9, 2008-04-28 ? i2c interface ? spi interface ?lf receiver ?rf encoder 2.3.2.4 power down state in power down state the cpu8051 and its peripherals are powered down. the system controller, its sfrs, the xdata memory and optional the lower 128 byte internal ram are kept powered. the lf receiver will be switched on periodically if the lf on/off timer is enabled. wakeup flags are cleared automatically when going to power down or thermal shutdown. wakeup events: a wakeup event occurs when a peripheral or external source causes the system to power up again. the wakeup source can be identified by reading sfrs wuf and extwuf. wakeup events may occur on following events: ? at least one of the external wakeup pins changed its state to the configured one ? interval timer underflow occured ? lf receiver carrier detected ? lf receiver pattern matched ? lf receiver sync matched ? watchdog timer elapsed 2.3.2.5 thermal shutdown state in thermal shutdown state, only the tmax circuit can provide a wakeup event. all other wakeup sources are disabled. the device will remain in this state until the temperature falls below the t rel threshold (see ?functional block description? on page 41 for details). targetdatasheet.book page 34 monday, april 28, 2008 11:16 am
preliminary data sheet 35 v0.9, 2008-04-28 PMA7110 functional description 2.3.2.6 state transitions with reference to figure 4 "normal mode - state transistion diagram" on page 31 , the following state transitions can occur: table 4 state transitions in normal mode state transition description run state => idle state (iflg) the application program can set sfr bit cfg0.5[idle] 1) to enter idle state. note that the next opcode should be a nop instruction. (see table 11 "sfr address f8 h : cfg0 - configuration register 0" on page 58 ) note: if no peripheral that can create a resume event is active, idle state will not be entered and the application will continue operation. idle state => run state (rs, irq) rs: a peripheral unit (timer 2, adc, rf transmitter, lf receiver, system clock source switch) creates a resume event. the application continues with the instruction after the idle bit setting (see table 20 "sfr address d1 h : ref - resume event flag register" on page 67 ). irq: an interrupt occurs. this interrupt allows the immediate execution of the interrupt service routine. with the return from interrupt instruction the device returns to idle state if no resume event has been generated in between. idle state => init state (wd) run state => init state (wd) overflow of the watchdog timer. the application will restart by initialization of the sfrs that are located outside the sfr container. no mode selection is possible, the normal mode is not left. the watchdog wakeup may be identified by table 18 "sfr address c0h: wuf - wakeup flag register" on page 65 run state => thermal shudown state (te) the application should enter thermal shutdown state whenever it detects that the specified operating temperature maximum of 125c has been overreached to avoid malfunction of the device. this is done by setting the cfg0.6 [tshdwn]. alternatively this can be done via rom library function. note: if the temperature is below the tmax threshold the device immediately generates a wu event and re-initializes the system run state => power down state (pdwn) entering this state is always software controlled by setting cfg0.7[pdwn]. the application program can call a rom library function to enter power down state whenever needed. targetdatasheet.book page 35 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 36 v0.9, 2008-04-28 thermal shutdown state => run state (wu) the tmax circuit generates a wakeup event when the temperature falls below tmax threshold. powerdownstate => run state (wu) a wakeup event will restart the application and set the sfr wuf resp. extwuf accordingly. the watchdog timer is re- initialized (see table 19 "sfr address f1h: extwuf - wakeup flag register 2" on page 65 ). wakeup duration from power down mode to run state typically lasts 1410 s. the time is the sum for the power supply to get stable (100s), the startup time of the oscillator (1150 s) and the time for the operating system to get initialized (160s @12mhz cpu8051 clock). init state => run state this state change is initiated automatically by the system controller as soon as init state is finished. 1) 1) note: it is mandatory that the instruction setting the cfg0.5[idle] is followed by a nop instruction. state transition description targetdatasheet.book page 36 monday, april 28, 2008 11:16 am
preliminary data sheet 37 v0.9, 2008-04-28 PMA7110 functional description 2.3.2.7 status of PMA7110 blocks in different states depending of the actual state in normal mode the internal blocks of the PMA7110 are active, inactive or have no supply to reduce power consumption. the next table gives an overview over the different blocks in the different device states. table 5 status of important PMA7110 blocks in different states peripheral unit run state idle state power down state thermal shutdown state power on reset active active active active brown-out detector active active inactive power down inactive power down power supply - low drop voltage regulator active active inactive power down (remark: can be enabled by lf-rx) inactive power down low power voltage supply active active active active system controller active active active active wakeup logic active active active active cpu8051 active inactive no supply no supply non-volatile sfrs (system controller) active inactive content not lost inactive content not lost inactive content not lost peripheral core sfr?s active inactive content not lost no supply - content lost no supply - content lost manchester/biphase coder, timer software selectable software selectable no supply no supply pheripheral modules - crc, mflsr software selectable inactive no supply no supply peripheral modules -i2c, spi, adc software selectable software selectable no supply no supply watchdog active active no supply no supply targetdatasheet.book page 37 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 38 v0.9, 2008-04-28 ram lower 128bytes active inactive content not lost selectable power down (content lost) or inactive (content not lost) selectable power down (content lost) or inactive (content not lost) ram upper 128bytes active inactive content not lost no supply - content lost no supply - content lost xdata 16 bytes active inactive content not lost inactive content not lost inactive content not lost flash memory active inactive content not lost no supply content not lost no supply content not lost rom active inactive no supply content not lost no supply content not lost crystal oscillator software selectable software selectable inactive power down inactive power down 2khz rc-oscillator active active active inactive power down 12mhz rc-hf-oscillator software selectable software selectable power down (remark: can be enabled by lf-rx) power down interval timer active active active inactive lf receiver software selectable software selectable software selectable inactive power down rf transmitter software selectable software selectable inactive power down inactive power down peripheral unit run state idle state power down state thermal shutdown state targetdatasheet.book page 38 monday, april 28, 2008 11:16 am
preliminary data sheet 39 v0.9, 2008-04-28 PMA7110 functional description vmin detector software selectable software selectable no supply inactive power down note: active : block is powered, is active and keeps its register contents. power consumption is high inactive : block is powered, cannot be used, but keeps its register contents. power consumtion is low no supply : block is not powered, connot be used and all register content is lost. power consumption is zero peripheral unit run state idle state power down state thermal shutdown state targetdatasheet.book page 39 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 40 v0.9, 2008-04-28 2.4 fault protection the PMA7110 features multiple fault protections which prevent the application from unexpected behavior and deadlocks. this chapter gives a brief overview of the available fault protections. detailed explanation of the usage can be found later in this document and in [1] ?reference sfr registers? on page 144 . 2.4.1 watchdog timer for operation security a watchdog timer is available to avoid application deadlocks. the watchdog timer must be reset periodically by the microcontroller, otherwise the timer generates a software reset and forces a restart of PMA7110 program execution. the watchdog timer duration is fixed to nominal 1 second. the accuracy depends on the accuracy of the 2 khz rc lp oscillator which is used to clock the watchdog timer. setting sfr bit cfg2.1[wdres] resets the watchdog timer (see table 13 "sfr address d8 h : cfg2 - configuration register 2" on page 60 ). 2.4.2 vmin detector this circuit will detect if the supply voltage is below the minimum value required to guarantee the measurement accuracy. the rom library functions which perform measurements will return the vmin status in a statusbyte with the measurement result. 2.4.3 flash memory checksum a crc checksum is stored in the flash memory, and can be recalculated and checked by the application program for verification of program code if needed. flash bit fcsp.7[eccerr]: if a single bit error in the flash memory occurs it is corrected by the flash internal error correction coder, as an indication the fcsp.7[eccerr] bit is set. (see table 101 "sfr address e9 h : fcsp- flash control register - sector protection control" on page 146 in ?reference sfr registers? on page 144 ) 2.4.4 adc measurement overflow & underflow the rom library functions which perform measurements will return the over/underflow status in a statusbyte with the measurement result. 2.4.5 tmax detector the tmax detector is used to wakeup the PMA7110 from thermal shutdown state if the ambient temperature falls below the trigger level t rel . entering thermal shutdown state can be initiated by a rom library function described in [1] ?reference documents? on page 157 . targetdatasheet.book page 40 monday, april 28, 2008 11:16 am
preliminary data sheet 41 v0.9, 2008-04-28 PMA7110 functional description 2.5 functional block description 2.5.1 sensor interfaces and data acquisition the PMA7110 has two internal sensors, two high sensitive differential analog interfaces 4 programmable gainfactors (from 76+-20%, 60+-20%, 50+-20% and 38+-20% ) and one standard differential analog interface (gainfactor 1) to acquire environmental data: ? temperature sensor ? battery voltage monitoring ? external data through analog interface the analog data is aquired and digitalized by the internal 10 bit adc. measurement routines for acquiring data are available within the rom library functions that are described in [1] ?reference documents? on page 157 . 2.5.1.1 sensor interface figure 6 block diagram sensor interface the sensor interface connects to the external sensors and to the internal (on-chip) temperature and battery voltage sensors. sfr adcdh sensor interface rd (sens.) v1n (sens.) vdd (sens.) v2n (sens.) vm2 (sens.) v2p (sens.) vm1 (sens.) v1p (sens.) vdd (sens.) temperature sensor a d c bandgap reference battery sensor control logic vreg sensor channel 3 channel 2 channel 1 amux2 amux1 sfr adcc1 subc[2:0] fcnsc gain[1:0] sfr adcdl data[7:0] data[9:8] sfr adcc0 stc[2:0] tvc[2:0] sfr adcs busy sample eoc cg3ff cl000 sarsath sarsatl sfr ref.5 readc sfr cfg1.3 adcen mux channel 0 channel 7 channel 6 channel 5 sfr adcm csi sfr adcoff off[5:0] sfr adcc1 gain[1:0] sfr adcm cs[2:0] rv[2:0] sfr cfg2.3 pdadc channel 4 ch0p,ch0n ch1p,ch1n ch4p,ch4n ch3p,ch3n ch2p,ch2n ch5p,ch5n ch6p,ch6n ch7p,ch7n standard sensor interface external sensor interface targetdatasheet.book page 41 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 42 v0.9, 2008-04-28 all signal channels can be configured for differential or single-ended operation. differential operation is only recommended for signals where the common-mode voltage is stable, while the positive and negative signal voltages vary symmetrically around the common-mode voltage. the input multiplexer selects one channel for the input signal and one channel for the reference voltage to the adc. any channel can be selected as reference, except channels 6 and 7, which are specially adapted to the low level signals from external sensors. targetdatasheet.book page 42 monday, april 28, 2008 11:16 am
preliminary data sheet 43 v0.9, 2008-04-28 PMA7110 functional description 2.5.1.2 two differential high sensitive interfaces to external sensors differential high sensitive sensor interface 1( (channel 6) v1p/v1n is the positve/negative differential voltage inputs of the first sensor bridge. differential high sensitive sensor interface 2 (channel 7) v2p/v2n is the positve/negative differential voltage inputs of the second sensor bridge. channel gain selection the sfr bit adcc1.5-4 [gain1-0] gain factor selection allows the selection of the sensitivity of the analog input channels 6 and 7. the gain is one for all other input channels (see table 6 ). table 6 selection of the gain factor sensor excitation the two sensor bridges have a common positive supply which is always connected. when a sensor bridge is to be activated, its negative supply is pulled to ground by pad vm1 or vm2 for vmp or vma. otherwise, it is disconnected. in this way the power of a connected bridge can be supplied. gain factor (gain) channel adcm.cs2-0 gain1 gain0 76 +/- 20% 11x 0 0 60 +/- 20% 11x 0 1 50 +/- 20% 11x 1 0 38 +/- 20% 11x 1 1 1others0 0 1others0 1 1others1 0 1others1 1 targetdatasheet.book page 43 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 44 v0.9, 2008-04-28 these two sensor interfaces are very adapted piezoresistive wheatstone bridge sensors, whose output signal is differential and ratiometric (proportional to the bridge excitation voltage). the electrical configuration is shown as a example in figure below.. figure 7 wheatstone bridge sensor 2.5.1.3 interface to other signals battery voltage interface (channel 0) the positive input to the battery voltage signal is derived by dividing voltage v bat by 3.5. the negative input is connected to gnd. the battery voltage is converted with a resolution of approximately 4.1mv, using channel 3 as reference. temperature sensor interface (channel 1) the temperature signal to the adc is a single ended signal, with the ptat voltage between 500 and 1100 mv. the temperature sensor signal is digitized with a resolution of approximately 0.5c, using channel 3 as reference. standard sensor interface (channel 2) the positive input signal is available at amux1, and the negative input at amux2. 2.5.1.4 reference voltages when channel 6 or 7 is selected as input to the adc, and the negative external sensor supply is identical to the negative supply of adc, this negative supply should be selected by the multiplexer as reference voltage on channel 5. rd v2n vm2 v2p vdd v1p vm1 v1n targetdatasheet.book page 44 monday, april 28, 2008 11:16 am
preliminary data sheet 45 v0.9, 2008-04-28 PMA7110 functional description if the negative external sensor supply (which should be used as reference voltage to external sensor) is not identical to the negative supply of adc, it should be connected to the channel 2 so that it can be selected by multiplexer as reference voltage for channel 6 or 7. but the supply voltage of the external sensor must always be within the range gnd to v batt figure 8 external sensor use channel 2 as reference voltage additional 3 channels on adc input multiplexer carry voltages which are intended as reference voltages for the converter: bandgap reference (channel 3) this reference is a nominal voltage of 1210 mv. it is intended as reference for the temperature and v bat measurements. vreg reference (channel 4) this reference is the v reg voltage. this is the largest allowable input voltage to the adc, and is meant as reference for the test signal, to allow as large test signal as possible. bridge supply reference (channel 5) when channel 6 or 7 is selected as input to the adc, the reference voltage is the bridge supply voltage. a multiplexer selects the appropriate negative bridge supply. PMA7110 sensor external supply voltage ch2p ch2n ch6p ch6n + - targetdatasheet.book page 45 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 46 v0.9, 2008-04-28 2.5.1.5 temperature sensor temperature measurement is performed by a dedicated rom library function. see ?temperature sensor characteristics? on page 128 for the sensor specification. 2.5.1.6 battery voltage monitor battery voltage measurement is performed by a dedicated rom library function. see ?battery sensor characteristics? on page 128 for the sensor specification. targetdatasheet.book page 46 monday, april 28, 2008 11:16 am
preliminary data sheet 47 v0.9, 2008-04-28 PMA7110 functional description 2.5.2 memory organization and special function registers (sfr) figure 9 memory map the following memory blocks are implemented: ? 12 kbyte rom memory ? 3 byte sfr mapped code memory ? 6 kbyte flash code memory ? 2x128 bytes flash user data memory ? 128 bytes flash configuration, id and reference cells ? 2 x 128 byte data ram / thereof 128 bytes battery buffered optionally ? 16 bytes battery buffered xdata ram nonvolatile code memory 0xffff not implemented 0x5880 0x587f 0x5800 user data sector i 0x57ff 0x5780 user data sector ii 0x577f code 0x4000 not implemented 0x3fff 0x3003 sfr mapped sram 0x3002 0x3000 0x2fff revision number, checksum mode handlers library functions vectors 0x0000 data memory 0xff sfr 0x80 0x7f 0x00 optional battery buffered data ram indirect addressing direct addressing data rom 12 kb flash 6kb ram 256 byte 0x58bf 0x5900 reference cells 6016b 128b 64b flash configuration + id 0x58c0 0x58ff 64b lockbyte 3 lockbyte 1 0x007f crc sum + lockbyt e 2 vectors 0x4033 xdata memory 0x0f 0x00 battery buffered data ram accessi bl e wi th movx ram 16 byte 128b targetdatasheet.book page 47 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 48 v0.9, 2008-04-28 2.5.2.1 rom a 12 kb rom memory is located in address range 0000 h to 2fff h . rom library functions and reset/wakeup handlers the rom contains the reset handler, the wakeup handler and the rom library functions (see [1] ?reference sfr registers? on page 144 ). a hardware mechanism is implemented to prevent direct jumping into the rom area, thus access to the rom library functions is granted via a vector table at the bottom of the rom address space. rom protection to protect the rom code against readout a hardware mechanism is implemented, thus a read operation from the rom in the protected address area returns zero. targetdatasheet.book page 48 monday, april 28, 2008 11:16 am
preliminary data sheet 49 v0.9, 2008-04-28 PMA7110 functional description 2.5.2.2 flash flash organization the flash is divided into five sectors. each sector can be erased and written individually (bytewise erasing and writing is not possible). ? 4000 h -- 577f h (6016 bytes) code sector (sector 0): this sector contains the code sector for the application program. ? 5780 h -- 587f h (2x128 bytes) user data sector i + user data sector ii (sector 1 + sector 2): these two sectors contain the user data sector which can store individual device configuration data. it also contains the crystal frequency which is needed for the rom library functions. ? 5880 h -- 58bf h (64 bytes) configuration sector (sector 3): this sector contains the flash configuration sector for flash driver parameters. ? 58c0 h -- 58ff h (64 bytes) reference cells sector (sector 4): this sector contains the reference current generator cells for flash reading. flash protection write and erase operations on the flash code sector are only allowed in programming mode. to protect the flash against unauthorized access three lockbytes can be set: ? lockbyte 1: address 0x58ff (top address of flash configuration + reference cells sector). this is written in the end of production test. whenever the resethandler detects this value the fcsp.0[conflock] gets set and the reference cells sector, flash configuration sector are irreversibly switched to read-only. ? lockbyte 2: address 0x577f (top address of the code sector). this byte is written (also a rom crc) by the programmer together with the code download. when the resethandler detects this byte it sets the fcsp.1[codelck]. in addition the debug mode, programming mode and test mode are no longer accessible. their pin settings lead to normal mode and reduced tm wherein the crc can be checked (pass/fail) and the whole flash can be erased to reset the chip to shipping state. this lockbyte has to be set during programming the code sector to protect application code against undesired read-out. ? lockbyte 3: address 0x587f (top address of the user data sector i and user data sector ii). there is a rom library function for setting this byte. (therefore the data in the user targetdatasheet.book page 49 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 50 v0.9, 2008-04-28 data sector have to be captured into ram, the lockbyte added, the whole sector erased (flash!) and re-written. whenever the resethandler detects this value dsr.0[flashlck] gets set. when not written together with the code sector the user data sector is planned to be written in normal mode (from the customer) using rom library functions. there is a hw mechanism that blocks access to the flash registers when operating from the flash (not rom). in this way, the usage of rom library functions is guaranteed, they ensure several important details not to damage the chip. if lockbyte 3 is set without setting lockbyte 2, this byte shows no effect and will result a unlocked flash. how to set lockbyte 3 is described in ?flash set lockbyte 3? on page 121 . targetdatasheet.book page 50 monday, april 28, 2008 11:16 am
preliminary data sheet 51 v0.9, 2008-04-28 PMA7110 functional description 2.5.2.3 ram the ram is available as data storage for the application program. rom library functions may use some ram locations for passing parameters and internal calculations. the ram area which is used for the rom library functions is specified in [1] ?reference documents? on page 157 . the ram is always powered in run state and idle state. the upper 128 bytes of ram are always switched off in power down state and thermal shutdown state and lose their contents in these states. sfr bit cfg2.4[pdlmb] determines if the lower 128 bytes of ram are powered during power down state and thermal shutdown state. if not powered in these states, this ram loses the content, otherwise it can be used as battery buffered storage beyond a power down period. note: the ram is not reset at a system reset. after a brown out reset this feature can be used to possibly recover data from ram. after power on reset the ram is not initialized, thus it contains random data. the application has to initialize the ram if needed. 2.5.2.4 special function registers special function registers are used to control and monitor the state of the PMA7110 and its peripherals. the following table shows the naming convention for the sfr descriptions that are used throughout this document. figure 10 naming convention for register descriptions note: if a single bit or the whole byte value is declared as unchanged, it keeps its state even during power down state or thermal shutdown state. table 7 "sfr special function register address overview" on page 53 shows all available registers of the PMA7110. note: all sfrs that are listed in table 7 "sfr special function register address overview" on page 53 but not in table 8 "status of sfr registers in r/c/w - 0/0 value after power on reset value after wakeup from power down / thermal shutdown stat e x ... unknown u ... unchanged 1 ... high 0 ... low access: r ... readable c ... cleared after read / automatically cleared w ... writeable targetdatasheet.book page 51 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 52 v0.9, 2008-04-28 power down state" on page 53 should not be changed by the application since they could be damaged irreversibly. these are handled automatically by the rom library functions if needed. targetdatasheet.book page 52 monday, april 28, 2008 11:16 am
preliminary data sheet 53 v0.9, 2008-04-28 PMA7110 functional description table 7 sfr special function register address overview the following tabe shows which sfrs keep their content in power down state and thermal shutdown state and gives a reference to the page within this document where a detailed description can be found. table 8 status of sfr registers in power down state addr register addr register addr register addr register addr register addr register addr register addr register f8 cfg0 f9 lfrxc fa fb fc fd fe ff f0 b f1 extwuf f2 extwum f3 spib f4 spic f5 spid f6 spim f7 spis e8 cfg1 e9 fcsp ea fcs eb p3dir ec p3in ed p3sens ee rfc ef lbd e0 acc e1 fcpp0 e2 fcpp1 e3 fcserm e4 fctkas e5 fcss e6 rfs e7 rfenc d8 cfg2 d9 dsr da adcoff db adcc0 dc adcc1 dd adwbc de rfvco df rffsld d0 psw d1 ref d2 adcm d3 adcs d4 adcdl d5 adcdh d6 oscconf d7 rffspll c8 tcon2 c9 tmod2 ca tl3 cb th3 cc tl2 cd th2 ce lfp1l cf lfp1h c0 wuf c1 wum c2 xtcfg c3 xtal1 c4 xtal0 c5 lfootp c6 lfoot c7 lfpcfg b8ip b9 divic baitpl bbitph bcitpr bdtmax belfpol bf lfpoh b0 p3out b1 i2cb b2 lfcdflt b3 lfdiv0 b4 lfdiv1 b5 lfcdm b6 lfrx1 b7 lfrx0 a8 ie a9 crcc aa crcd ab rngd ac crc0 ad crc1 ae rftx af lfsyncfg a0 p2 (reserved) a1 p2dir (reserved) a2 i2cc a3 i2cm a4 lfrxs a5 lfrxd a6 lfsyn0 a7 lfsyn1 98 scon (reserved) 99 sbuf (reserved) 9a i2cd 9b i2cs 9c dbcl1 9d dbch1 9e dbtl1 9f dbth1 90 p1out 91 p1dir 92 p1in 93 p1sens 94 dbcl0 95 dbch0 96 dbtl0 97 dbth0 88 tcon 89 tmod 8a tl0 8b tl1 8c th0 8d th1 8e rfd 8f irqfr 80 p0 (reserved) 81sp 82dpl 83dph 84mmr0 85mmr1 86mmr2 87pcon sfr (abbr.) addr register description power supply description page vddd vddc note: acc 0xe0 accumulator n page 57 adcc0 0xdb adc configuration register 0 n page 144 adcc1 0xdc adc configuration register 1 n page 144 adcdl 0xd4 adc result register (low byte) n page 151 adcdh 0xd5 adc result register (high byte) n page 151 . adcm 0xd2 adc mode register n page 145 . adcoff 0xda adc input offset c-network configuration n page 145 . adcs 0xd3 adc status register n page 146 . adwbc 0xdd ad wbc wire bond check n page 146 . b 0xf0 register b n page 57 . cfg0 0xf8 configuration register 0 n page 58 cfg1 0xe8 configuration register 1 n page 59 cfg2 0xd8 configuration register 2 n page 60 crcc 0xa9 crc control register n page 87 crcd 0xaa crc data register n page 151 crc0 0xac crc shift register (low byte) n page 151 crc1 0xad crc shift register (high byte) n page 152 targetdatasheet.book page 53 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 54 v0.9, 2008-04-28 dbcl0 0x94 cpu debug compare register 0 (low) n page 152 dbch0 0x95 cpu debug compare register 0 (high) n page 152 dbtl0 0x96 cpu debug target register 0 (low) n page 152 dbth0 0x97 cpu debug target register 0 (high) n page 152 dbcl1 0x9c cpu debug compare register 1 (low) n page 152 dbch1 0x9d cpu debug compare register 1 (high) n page 152 dbtl1 0x9e cpu debug target register 1 (low) n page 153 dbth1 0x9f cpu debug target register 1 (high) n page 153 divic 0xb9 internal clock divider n page 71 dpl 0x82 data pointer (low) n page 57 dph 0x83 data pointer (high) n page 57 dsr 0xd9 diagnosis and status register n page 60 extwuf 0xf1 wakeup flag register 2 n page 65 extwum 0xf2 wakeup mask register 2 n page 65 fcsp 0xe9 flash control register - sector protection control n page 146 fcs 0xea flash control register - status mode n page 147 . fcpp0 0xe1 flash charge pumps power control register 0 n page 147 fcpp1 0xe2 flash charge pumps power control register 1 n page 147 fcserm 0xe3 flash sector erase and read margin select register n page 148 . fctkas 0xe4 flash tkill and analog output select register n page 153 fcss 0xe5 flash control register for single-step mode n page 154 i2cb 0xb1 i2c baudrate register n page 112 i2cc 0xa2 i2c control register n page 111 i2cd 0x9a i2c data register n page 112 i2cm 0xa3 i2c mode register n page 113 i2cs 0x9b i2c status register n page 112 ie 0xa8 interrupt enable register n page 76 ip 0xb8 interrupt priority register n page 77 irqfr 0x8f interrupt request flag register (for extended interrupts) n page 77 itpl 0xba interval timer precounter register (low byte) n page 69 itph 0xbb interval timer precounter register (high byte) n page 69 itpr 0xbc interval timer period register n page 68 lbd 0xef low battery detector control n page 154 lfcdflt 0xb2 t.b.d n t.b.d lfcdm 0xb5 t.b.d n t.b.d lfdiv0 0xb3 t.b.d n t.b.d lfdiv1 0xb4 t.b.d n t.b.d lfoot 0xc6 t.b.d n t.b.d lfootp 0xc5 t.b.d n t.b.d lfpcfg 0xc7 t.b.d n t.b.d lfp0l 0xbe t.b.d n t.b.d lfp0h 0xbf t.b.d n t.b.d lfp1l 0xce t.b.d n t.b.d sfr (abbr.) addr register description power supply description page vddd vddc note: targetdatasheet.book page 54 monday, april 28, 2008 11:16 am
preliminary data sheet 55 v0.9, 2008-04-28 PMA7110 functional description lfp1h 0xcf t.b.d n t.b.d lfrx0 0xb7 t.b.d n t.b.d lfrx1 0xb6 t.b.d n t.b.d lfrxc 0xf9 t.b.d n t.b.d. lfrxd 0xa5 t.b.d n t.b.d lfrxs 0xa4 t.b.d n t.b.d. lfsyncfg 0xaf t.b.d n t.b.d. lfsyn0 0xa6 t.b.d n t.b.d lfsyn1 0xa7 t.b.d n t.b.d mmr0 0x84 memory mapped register 0 n page 148 mmr1 0x85 memory mapped register 1 n page 148 mmr2 0x86 memory mapped register 2 n page 150 oscconf 0xd6 rc hf oscillator configuration register n page 155 p0 (reserved) 0x80 io-port 0 data register n.u. p1dir 0x91 io-port 1 direction register n page 106 p1in 0x92 io-port 1 data in register n page 107 p1out 0x90 io-port 1 data out register n page 106 p1sens 0x93 io-port 1 sensitivity register n page 107 p3dir 0xeb io-port 3 direction register n page 106 p3in 0xec io-port 3 data in register n page 107 p3out 0xb0 io-port 3 data out register n page 106 . p3sens 0xed io-port 3 sensitivity register n page 107 p2 (reserved) 0xa0 io-port 2 data register n.u. p2dir (reserved) 0xa1 io-port 2 direction register n.u. pcon (reserved) 0x87 power control register n.u. psw 0xd0 program status word n page 57 ref 0xd1 resume event flag register n page 67 rfc 0xee rf-transmitter control register n page 79 rfd 0x8e rf-encoder tx data register n page 82 rfenc 0xe7 rf-encoder tx control register n page 82 rffspll 0xd7 rf-frequency synthesizer pll configuration n page 155 . rfs 0xe6 rf-encoder tx status register n page 84 rffsld 0xdf rf-frequency synthesizer lock detector configuration n page 151 rftx 0xae rf-transmitter configuration register n page 79 rfvco 0xde rf-frequency synthesizer vco configuration n page 151 rngd 0xab rng data register n page 89 sbuf (reserved) 0x99 serial interface buffer n.u. scon (reserved) 0x98 serial interface control register n.u. sp 0x81 stack pointer n page 149 . spib 0xf3 spi baudrate register (11 bit cascaded register) n page 117 spic 0xf4 spi control register n page 115 spid 0xf5 spi data register n page 116 spim 0xf6 spi mode register n page 116 sfr (abbr.) addr register description power supply description page vddd vddc note: targetdatasheet.book page 55 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 56 v0.9, 2008-04-28 spis 0xf7 spi status register n page 116 tcon 0x88 timer control register (timer 0/1) n page 92 tcon2 0xc8 timer control register 2 (timer 2/3) n page 93 th0 0x8c timer 0 register high byte n page 150 th1 0x8d timer 1 register high byte n page 149 th2 0xcd timer 2 register high byte n page 150 th3 0xcb timer 3 register high byte n page 150 tl0 0x8a timer 0 register low byte n page 150 tl1 0x8b timer 1 register low byte n page 150 tl2 0xcc timer 2 register low byte n page 150 tl3 0xca timer 3 register low byte n page 150 tmod 0x89 timer mode register n page 90 tmod2 0xc9 timer mode register 2 (timer 2/3) n page 91 tmax 0xbd tmax detector control n page 156 wuf 0xc0 wakeup flag register n page 65 wum 0xc1 wakeup mask register n page 64 xtal0 0xc4 xtal frequency register (fsklow) n page 73 xtal1 0xc3 xtal frequency register (fskhigh/ask) n page 73 xtcfg 0xc2 xtal configuration register n page 72 note: power supply vddc switched off during power down state register value will be lost. sfr (abbr.) addr register description power supply description page vddd vddc note: targetdatasheet.book page 56 monday, april 28, 2008 11:16 am
preliminary data sheet 57 v0.9, 2008-04-28 PMA7110 functional description 2.5.3 microcontroller central part of the PMA7110 is an cpu8051 instruction set compatible microcontroller. the cpu8051 offers an 8-bit datapath, an interrupt controller, several addressing modes (direct, register, register indirect, bit direct), and accesses peripheral components using special function registers (sfr). the architecture of the cpu8051 is well known and not part of this discription. however some of the features are not needed or adapted to special product requirements. these features are described herein in detail. the cpu8051 incorporates basic core internal registers. accumulator (acc), register b (b) and program status word (psw) are bitaddressable registers used to perform arithmetical and logical operations. stack pointer (sp) and data pointer (dpl/dph) are included to allow basic programming structures. table 9 8051 basic sfrs sfr psw holds the result of basic arithmetic operations. table 10 sfr address d0 h : psw - program status word sfr (abbr) addr access default value register acc e0 h rw 00 h /00 h accumulator b f0 h rw 00 h /00 h register b dpl 82 h rw 00 h /00 h data pointer (low) dph 83 h rw 00 h /00 h data pointer (high) psw d0 h rw 00 h /00 h program status word sp 81 h rw 00 h /00 h stack pointer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cy ac f0 rs1 rs0 ov f1 p rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 r 0/0 cy carry bit; set to '1' if accumulator changes signed number range through 0x00/0xff (unsigned range overflow) ac auxillary carry bit; carry-out for bcd operations. f0 general purpose bit 0; may be freely used by the application rs1 register bank select; bit 1 rs0 register bank select; bit 0 ov overflow bit; set to '1' if accu changes signed number range through 0x80/0x7f with arithmetic operations (signed range overflow) f1 gereral purpose bit 1; may be freely used by the application p reflects the number of 1s in the accumulator (set to '1' if accu contains an odd number of 1s) targetdatasheet.book page 57 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 58 v0.9, 2008-04-28 2.5.4 system configuration registers the system configuration registers can be used for: ? initiating state transitions ? system software reset ? enabling or disabling peripherals ? monitoring the operation mode, the system state and peripherals table 11 sfr address f8 h : cfg0 - configuration register 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pdwn tshdwn idle n.u. ftm n.u. n.u. clksel0 rw 0/0 rw 0/0 rw 0/0 r 0/0 rw u/0 r 0/0 r 0/0 rw 0/0 pdwn power down state if set to ?1? by software the power down state is entered; this bit is automatically reset to ?0? by the system controller after a wakeup. note: entering power down state is handled by a rom library function. it is not recommended to set this bit manually. tshdwn thermal shutdown state if set to ?1? by software the thermal shutdown state is entered; this bit is automatically reset to '0' by the system controller after wakeup. note: entering thermal shutdown state is handled by a rom library function. it is not recommended to set this bit manually. idle idle state if set to ?1? by software the idle state is entered; this bit is automatically reset to ?0? by the system controller after a resume event occurred. ftm only used for internal production test mode, don?t care for application clksel0 systemclock source select 1: select crystal oscillator clock 0: select 12mhz rc hf oscillator note: changing the systemclock is handled by a rom library function. it is not recommended to set this bit manually. targetdatasheet.book page 58 monday, april 28, 2008 11:16 am
preliminary data sheet 59 v0.9, 2008-04-28 PMA7110 functional description table 12 sfr address e8 h : cfg1 - configuration register 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pmwen i2cen rftxpen adwben spien itinit iten rw 0/0 rw 0/0 r 0/0 rw u/0 rw 0/0 rw 0/0 r 0/0 r u/1 pmwen program memory write enable. this bit is only used for programming mode: 0: no write access to flash program memory 1: write access to flash program memory is allowed note: this bit is under control of rom library functions. don?t care for application. i2cen i 2 c enable 1: i 2 c behavior on pins pp1/scl and pp2/sda is enabled 0: keeps standard i/o-port functionality rftxpen transmitter data port out enable 1: the transmission data is strobed on port pp2/txdata 0: gpio port functionality is provided. adwben adc conversion enable. this is under control of rom library functions. don?t change this bit by the application manually. itinit interval timer initialization active this bit is ?1? as long as the interval-timer is configured with the content of the itpr register. this bit is automatically cleared after initialization completes. iten intervaltimer enable (test-, debug-, progmode only) targetdatasheet.book page 59 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 60 v0.9, 2008-04-28 table 13 sfr address d8 h : cfg2 - configuration register 2 table 14 sfr address d9 h : dsr -diagnosis and system status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 enhfbyp n.u. n.u. pdlmb pdadc n.u. wdres reset rw 0/0 r 0/0 r 0/0 rw u/1 rw 1/1 r 0/0 cw 0/0 cw 0/0 enhfbyp enable rf vreg-hf bypass pdlmb power down ram lower memory block (00 h - 7f h ) 1: the lower 128 byte ram is powered down in power down state or thermal shutdown state 0: the lower memory block is always powered. pdadc power down adc 1: adc no supply 0: adc active note: this bit is handled by the rom library functions automatically. it is not recommended to change this bit manually. wdres reset watchdog counter to 0 reset reset system (software reset) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sclk tmax opmode1 opmode0 flashcp1 flaschcp0 wup flashlck r 0/0 r x/x r u/x r u/x r 0/0 r 0/0 r x/0 rmw u/0 sclk status flag indicating the current systemclock. 1: crystal oscillator clock 0: 12 mhz rc hf oscillator tmax tmax detector status bit 1: temperature < tmax 0: temperature > tmax this bit should be polled by the application before entering thermal shutdown state note: entering thermal shutdown state is handled by a rom library function. it is not needed to evaluate this bit manually. opmode0-1 these bits indicate the current operation mode 11b: normal mode 10b: programming mode 01b: debug mode 00b: internal productiontest mode flashcp1 only used for internal production test mode, don?t care for application flashcp0 only used for internal production test mode, don?t care for application wup wakeup pending flashlck flash lock (0=full flash-sfr access, 1=restricted write access) it is set to '1' by sw if config-magic-number is detected. self-holding when '1'! targetdatasheet.book page 60 monday, april 28, 2008 11:16 am
preliminary data sheet 61 v0.9, 2008-04-28 PMA7110 functional description 2.5.5 general purpose registers (gpr) in PMA7110, xdata memory gpr1 - gprf are used in normal-, debug- and programming mode as 16 gpr-general purpose register, which can be used by the application to store data beyond a power down state period. they consume low leakage current compared to the whole lower memory block by storing low amounts of data. they can also be used as testmode-registers in functional testmode for building blocks and test-hardware, but they are not reseted in these modes to allow data retention even after brown-out. table 15 gpr registers note: the gprs are in the xdata area and therefore not reset on a system reset. after a brownout reset this feature can be used to possibly recover data from ram. after power on reset the gpr registers are not initialzed, thus they contain random data. the application has to initialize the gpr registers if needed. sfr (abbr) addr register gpr0 0x00 xdata general purpose register 0 gpr1 0x01 xdata general purpose register 1 gpr2 0x02 xdata general purpose register 2 gpr3 0x03 xdata general purpose register 3 gpr4 0x04 xdata general purpose register 4 gpr5 0x05 xdata general purpose register 5 gpr6 0x06 xdata general purpose register 6 gpr7 0x07 xdata general purpose register 7 gpr8 0x08 xdata general purpose register 8 gpr9 0x09 xdata general purpose register 9 gpra 0x0a xdata general purpose register 10 gprb 0x0b xdata general purpose register 11 gprc 0x0c xdata general purpose register 12 gprd 0x0d xdata general purpose register 13 gpre 0x0e xdata general purpose register 14 gprf 0x0f xdata general purpose register 15 targetdatasheet.book page 61 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 62 v0.9, 2008-04-28 2.5.6 system controller while the microcontroller controls PMA7110 in run state, the system controller takes over control in power down state, idle state and thermal shutdown state. the system controller handles the system clock, wakeup events, and system resets. figure 11 block diagram of the system controller 2.5.6.1 wakeup logic one of the key elements within the system controller is the wakeup logic, which is responsible for transitions from power down state to run state via init state. the wakeup logic is clocked by the 2 khz rc lp oscillator, thus the wakeup logic is fully functional even when all other clock sources (12 mhz rc hf oscillator and crystal oscillator) are switched off. wakeup logic power management system controller sfr registers delay timer reset handler timer calibration unit lf on/off timer interval timer io-port control clock controller i/o port clock divider intern por rf-transmitter lf-receiver resume wakeup wakeup resume en power supply sensor interface adc resume on/off timer wakeup en en sy ste m clock system reset 12mhz rc-hf- oscillator 2khz rc-lp- oscillator interval timer crystal oscillator wa ke up temp. sensor v supply sensor 2x high sensitive differential 1x standard differential analog interfaces targetdatasheet.book page 62 monday, april 28, 2008 11:16 am
preliminary data sheet 63 v0.9, 2008-04-28 PMA7110 functional description the difference between reset and wakeup: ? reset - either via software reset, brownout or reset pin, the digital circuit is reset. program execution starts at address 0000 h to perform reset initialization routines (including operation mode selection) and will jump to the flash at address 4000 h in normal mode to execute the application program. ? wakeup - only the program counter of the microcontroller and its peripheral units are reset. program execution starts at address 0000 h to perform wakeup initialization routines (for evaluating the wakeup source) and jumps to the flash at 4000 h to execute the application program. wakeup event handling whenever a wakeup event occurs, the PMA7110 leaves power down state and enters run state to execute the application code. this transition can be initiated from various sources. the wakeup source can be identified by reading sfr wuf and sfr extwuf. a wakeup source can be enabled or disabled by setting the appropriate bits in sfr wum and sfr extwum. for security reasons the interval timer wakeup cannot be masked and the interval timer can not be disabled. the watchdog, which is only active in run and idle state can not be masked. sfr wuf and sfr extwuf are read-only, thus no set/clear operations are possible. the wakeup source (except the watchdog) is available during the whole run state. if an additional wakeup event occurs during run state, the appropriate flag will be set, but the device won?t be forced through init state. it won?t be cleared until power down state is entered again. targetdatasheet.book page 63 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 64 v0.9, 2008-04-28 table 16 sfr address c1 h : wum - wakeup mask registerm bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mwdog mtmax mlfcd mlfsy mlfpm1 mlfpm0 n.u. mitim rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 mwdog mask watchdog wakeup watchdog wakeup is not maskable in normal mode this bit is only used for internal production test mode,debug- and prog. mode. don?t care for application mtmax mask tmax wakeup tmax wakeup is not maskable in normal mode this bit is only used for internal production test mode,debug- and prog. mode. don?t care for application mlfcd mask lf receiver carrier detect 0: no mask (enable wakeup source) 1: mask (disable wakeup source) mlfsy mask lf receiver sync match 0: no mask (enable wakeup source) 1: mask (disable wakeup source) mlfpm1 mask lf receiver pattern 1 match 0: no mask (enable wakeup source) 1: mask (disable wakeup source) mlfpm0 mask lf receiver pattern 0 match 0: no mask (enable wakeup source) 1: mask (disable wakeup source) itim mask interval timer wakeup interval timer wakeup is not maskable in normal mode this bit is only used for internal producti on test mode, don?t care for application targetdatasheet.book page 64 monday, april 28, 2008 11:16 am
preliminary data sheet 65 v0.9, 2008-04-28 PMA7110 functional description table 17 sfr address f2 h : extwum - wakeup mask register 2 table 18 sfr address c0 h : wuf - wakeup flag register table 19 sfr address f1 h : extwuf - wakeup flag register 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mextwu7 mextwu6 mextwu5 mextwu4 mextwu3 mextwu2 mextwu1 mextwu0 rw u/1rw u/1rw u/1rw u/1rw u/1rw u/1rw u/1rw u/1 mextwu7 mask external wakeup 7 mextwu6 mask external wakeup 6 mextwu5 mask external wakeup 5 mextwu4 mask external wakeup 4 mextwu3 mask external wakeup 3 mextwu2 mask external wakeup 2 mextwu1 mask external wakeup 1 mextwu0 mask external wakeup 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdog tmu lfcd lfsy lfpm1 lfpm0 n.u. itim rc x/0 rc x/0 rc x/0 rc x/0 rc x/0 rc x/0 r 0/0 rc x/0 wdog watchdog wakeup tmu tmax underflow wakeup lfcd lf receiver carrier wakeup lfsy lf receiver sync match wakeup lfpm1 lf receiver pattern 1 match wakeup lfpm0 lf receiver pattern 0 match wakeup itim interval timer wakeup bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extwu7 extwu6 extwu5 extwu4 e xtwu3 extwu2 extwu1 extwu0 r x/0 r x/0 r x/0 r x/0 r x/0 r x/0 r x/0 r x/0 extwu7 external wakeup 7 extwu6 external wakeup 6 extwu5 external wakeup 5 extwu4 external wakeup 4 extwu3 external wakeup 3 targetdatasheet.book page 65 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 66 v0.9, 2008-04-28 watchdog wakeup a watchdog wakeup occurs after the watchdog timer has elapsed. see ?watchdog timer? on page 40 for details about the watchdog timer. tmax wakeup a tmax wakeup occurs only if the device was in thermal shutdown state and the temperature falls below the threshold temperature t rel . see ?functional block description? on page 41 for details about the tmax wakeup. lf receiver wakeup event the lf receiver wakeup can be enabled by setting either: ? sfr bit wum.5 [lfcd] or ? sfr bit wum.4 [lfsy] or ? sfr bit wum.3[lfpm1] and/or sfr bitwum.2 [lfpm0] the wakeup source can be read in the sfr wuf. note: the lf receiver has to be configured appropriate for the particular wakeup modes. see ?lf receiver? on page 85 for details. external wakeup event i/o port pp1-pp4 and pp6-pp9 can be configured to wakeup the PMA7110 from power down state by an external source. note: pp1-pp4 and pp6-pp9 have to be configured according to ?external wakeup on pp1-pp4 and pp6-pp9? on page 109 for this feature. interval timer wakeup event when the interval timer elapses, a wakeup event is generated and power down state is left. the wakeup can be identified by the application software reading sfr bit wuf.0[itim]. the interval timer is reloaded automatically with actual values from register itpr and immediately restarted, so the interval timer is even working in run state. note: the interval timer is not maskable, so the application will get interval timer wakeup events periodically. if these wakeup events occur during run state, they will set the appropriate flag but not force the device through init state. extwu2 external wakeup 2 extwu1 external wakeup 1 extwu0 external wakeup 0 targetdatasheet.book page 66 monday, april 28, 2008 11:16 am
preliminary data sheet 67 v0.9, 2008-04-28 PMA7110 functional description idle state and resume event handling if switched to idle state by setting sfr bit cfg0.5 [idle], the systemclock to the microcontoller is gated off. note: idle state will only be entered if one of the units providing a resume event is enabled and active. otherwise the system will continue executing code in run state without entering idle state. only few peripherial components are still active in idle state. the watchdog is active and will be initialized automatically before entering idle state, thus idle state has a maximum duration of approx. 1 second before a watchdog wakeup occurs. the systemclock to the microcontroller is re-enabled when a resume event occurs. the program code continues working where it was suspended. sfr bit cfg0.5[idle] is automatically cleared after a resume event. the resume event source is available in sfr ref. the idle state will be left in case an interrupt event occurrs. after completion of the interrupt service the idle state will be re-entered in case no resume event is pending. table 20 sfr address d1 h : ref - resume event flag register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rextg n.u. readc relfo rerfu rerff rerc ret2 rc 0/0 0/0 rc 0/0 rc 0/0 rc 0/0 rc 0/0 rc 0/0 rc 0/0 rextg systemclock changed to crystal the PMA7110 can be put into idle state during crystal startup. after expiring of the crystal delay time the rextg flag is set. (see also sfr xtcfg.2-0 bit xtdly[2-0] in table 26 "sfr address c2 h : xtcfg - crystal config register" on page 72 ). readc adc conversion complete (this bit is under control of rom library functions relfo lf receiver buffer full rerfu rf transmit buffer empty rerff rf transmission finished rerc 2 khz rc lp oscillator calibration complete ret2 timer 2 underflow targetdatasheet.book page 67 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 68 v0.9, 2008-04-28 2.5.6.2 interval timer figure 12 interval timer block diagram the interval timer is responsible to wakeup the PMA7110 from the power down state after a predefined time interval. it is clocked by the 2khz rc lp oscillator and incorporates two dividers: ? precounter: can be calibrated to the systemclock and represents the timebase. ? postcounter: configures the interval timer duration. it can be set from 1-256 dec . timing accuracy can be ensured by using a rom library function which calibrates the precounter towards the accurate systemclock. see [1] ?reference documents? on page 157 . the interval timer duration is determined by the sfr itpr. this value is calculated by using the following equation: the postcounter (itpr) is an 8 bit register. the maximum interval duration corresponds to 00 h (multiplication with 256 dec ). 01 h up to ff h corresponds to a multiplication with 1 dec up to 255 dec . note: after writing sfr itpr some clock cyles are needed to activate the new setting. sfr bit cfg1.1[itinit] is cleared automatically when the new setting is activated. table 21 sfr address bc h: itpr - interval timer period register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 itpr.7 itpr.6 itpr.5 itpr.4 itpr.3 itpr.2 itpr.1 itpr.0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/1 interval timer 2khz rc lp oscillator (uncalibrated) precounter itfsl [7:0] itfsh [11:8] postcounter itpr [7:0] interval wakeup intervaltimeriod s [] precounter f 2khzrclposcillator 1 s -- - --------------------------------------------------------- postcounter ? = targetdatasheet.book page 68 monday, april 28, 2008 11:16 am
preliminary data sheet 69 v0.9, 2008-04-28 PMA7110 functional description 2.5.6.3 interval timer calibration calibration is done by counting clock cycles from the crystal oscillator or the 12mhz rc hf oscillator (depending on the current systemclock) during one 2khz rc lp oscillator period. the calibration is performed automatically by a rom library function (see [1] ?reference documents? on page 157 ). note: if the crystal oscillator should be used for the calibration, the crystal frequency has to be stored in the flash user data sector. table 22 sfr address ba h : itpl- interval timer precounter (low byte) table 23 sfr address bb h : itph- interal timer precounter (high byte) note: these sfrs can be modified manually as well for using other (uncalibrated) precounter values. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 itp.7 itp.6 itp.5 itp.4 itp.3 itp.2 itp.1 itp.0 rw u/1 rw u/1 rw u/1 rw u/0 rw u/1 rw u/0 rw u/0 rw u/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. itp.11 itp.10 itp.9 itp.8 0/0 0/0 0/0 0/0 rw u/0 rw u/0 rw u/1 rw u/1 targetdatasheet.book page 69 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 70 v0.9, 2008-04-28 2.5.7 clock controller the clock controller for internal clock managment is part of the system controller. the PMA7110 always starts up using the 12 mhz rc hf oscillator to provide minimum startup time and minimum current consumption. changing the systemclock from the 12 mhz rc hf oscillator to the crystal (e.g. for rf transmisssion) is performed automatically by a rom library function (see [1] ?reference documents? on page 157 ). if the crystal is selected as systemclock, the 12 mhz rc hf oscillator is automatically powered down. note: since the external crystal needs some startup time, a 3 bit delay timer is integrated to delay the clock switching. dependent on the used crystal the sfr bits xtcfg.2-0 [xtdly2-0] can be set to delay from typ. 0s up to 1750s in 250s steps.(see table 26 "sfr address c2 h : xtcfg - crystal config register" on page 72 ). the following figure shows which clocks are used for which PMA7110 blocks. details about the individual blocks can be found in the appropriate chapters of this document figure 13 PMA7110 clock concept 12 mhz rc hf oscillator crystal oscillator 19,6875 mhz 18,080 mhz 18,08958 mhz 19,0625 mhz 2 khz rc lp oscillator : 2 sfr divic :64/:16/:4/:1 rf transmitter (pll, vco) sfr cfg0 clksel sfr tmod interval timer precounter sfr itfsl/h postcounter sfr itpr pp2 / event lf on/off timer precounter sfr lfootp on/off counter sfr lfoot : 8 lf baudrate generator sfr lfdiv data recovery synconizer timer baudrate generator rf encoder general purpose timer timer for lf baudrate calibration microcontroller cpu crc generator/ checker pseudo random number generator targetdatasheet.book page 70 monday, april 28, 2008 11:16 am
preliminary data sheet 71 v0.9, 2008-04-28 PMA7110 functional description PMA7110 internal clock divider for power saving it is possible to enable the internal clock divider, to reduce the systemclock by a prescaled factor. if sfr divic is set to 00 h (default) the divider is disabled. table 24 sfr address b9 h : divic - internal clock divider 2.5.7.1 2 khz rc lp oscillator (low power) the 2 khz rc lp oscillator stays active even in power down state. the typical frequency of the oscillator is 2khz. 2.5.7.2 12 mhz rc hf oscillator (high frequency) the 12 mhz rc hf oscillator runs at typ. 12mhz. it is used as the default clock source for the PMA7110 in run state and is calibrated in the infineon production site. 2.5.7.3 crystal oscillator the crystal oscillator is a negative impedance converter (nic) oscillator with a crystal operating in series resonance. the nominal crystal operating frequencies are between 18mhz and 20mhz depending on the rf-band used. table 25 formulas for crystal selection dependent of rf- bands bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. divic1 divic0 0/0 0/0 0/0 0/0 0/0 0/0 rw u/0 rw u/0 divic1-0 ?internal clock divider? 11b: divide by 64 10b: divide by 16 01b: divide by 4 00b: divide by 1 868mhz 915mhz f xtal , f rf 1 48 ----- - ? = 434mhz f xtal f rf 2 48 ----- - ? = 315mhz f xtal f rf 3 48 ----- - ? = targetdatasheet.book page 71 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 72 v0.9, 2008-04-28 crystal startup time adjustment for different crystals is possible in steps of 250s by using the sfr bits xtcfg.2-0 [xtdly2-0]. table 26 sfr address c2 h : xtcfg - crystal config register frequency pulling from the nominal crystal frequency can be achieved by the internal capacitor banks. this can be used for fine tuning the ask carrier frequency and the lower and upper modulation frequencies for fsk modulation. thus, frequency errors due to crystal or component tolerances can be trimmed away. figure 14 crystal oscillator and fsk-modulator block diagram the sfrs sfr xtal0 and sfr xtal1 allow the trimming of the crystal frequency in a broad range. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. xtdly2 xtdly1 xtdly0 0/0 0/0 0/0 0/0 0/0 rw u/0 rw u/1 rw u/1 xtdly2-0 crystal delay timer delay time in steps of 250s @ typ. 2 khz rc lp oscillator clcok = 2khz 111b: typ. 1750s 110b: typ. 1500s 101b: typ. 1250s 100b: typ. 1000s 011b: typ. 750s 010b: typ: 500s 001b: typ. 250s 000b: typ. 0s crystal oscillator c 18 - 20 mhz xtal xcap 8 fsk-modulator xgnd 8bit data sfr xtal1 8bit data sfr xtal0 fsk data targetdatasheet.book page 72 monday, april 28, 2008 11:16 am
preliminary data sheet 73 v0.9, 2008-04-28 PMA7110 functional description table 27 sfr address c4 h : xtal0 - xtalconfiguration register (fsklow) table 28 sfr address c3 h : xtal1-xtal config. register (fskhigh/ask) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fsklow7 fsklow6 fsklow5 fsklow4 fsklow3 fsklow2 fsklow1 fsklow0 w u/1 w u/1 w u/1 w u/1 w u/1 w u/1 w u/1 w u/1 fsklow7-0 fsk low frequency capacitor select for lower fsk modulation frequency if rfenc.3==0[txdd] and if rftx.5==0[askfsk]. the capacitor array is binary weighted from fsklow7 = 20pf (msb) fsklow0 = 156ff (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fskhask7 fskhask6 fskhask5 fskhask4 fskhask3 fskhask2 fskhask1 fskhask0 w u/1 w u/1 w u/1 w u/1 w u/1 w u/1 w u/1 w u/1 fskhask7-0 fsk high frequency / ask centre frequency capacitor select for upper fsk modulation frequency if rfenc.3===1[txdd] and if rftx.5==0[askfsk] or ask center frequency fine tuning capacitor select if rftx.5==1[askfsk]. the capacitor array is binary weighted from fskhask7 = 20pf (msb) down to fskhask0 = 156ff (lsb). targetdatasheet.book page 73 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 74 v0.9, 2008-04-28 2.5.8 interrupt sources on the similar to the cpu8051 the supports interrupt events of several sources which are listed below. when an interrupt occurs the pc is automatically set to the vector assigned to the interrupt source. from there the vector is forwarded via ljmp instruction into the flash area and the offset of 4000 h is added. when an an unmasked interrupt occurs while the device is in idle state this state is immediately left and the pc continues operation on the appropriate interrupt vector (see figure 29 ). after the processing of the interrupt service routine ( reti instruction) the device automatically returns into idle state in case no resume event has occured in between. if a resume event has been detected during the interrupt service routine the reti instruction returns the pc to the location after the idle instruction. it is highly recommended that this instruction to be a nop . the priority of the interrupts can be configured using the ip register. setting a bit in ip to one assigns higher priority to the linked interrupt. a high priority interrups can then interrupt a service routine from a low priority interrupt. table 29 interrupt vector locations interrupt vector vector address forwarded address interrupt source reset vector 00 h 4000 h vector 0 03 h 4003 h external interrupt 0 (pp9) vector 1 0b h 400b h timer 0 interrupt vector 2 13 h 4013 h external interrupt 1 (pp7) vector 3 1b 401b timer 1 interrupt vector 4 23 h 4023 h i2c interface interrupt vector 5 2b h 402b h spi interface interrupt vector 6 33 h 4033 h extended interrupt: the flash software has to detect the interrupt source peripheral from this vector by reading irqfr and the appropriate source within the peripheral from the various flag registers. ? timer 2 interrupt ? timer 3 interrupt ? lf receiver interrupt ? rf encoder interrupt targetdatasheet.book page 74 monday, april 28, 2008 11:16 am
preliminary data sheet 75 v0.9, 2008-04-28 PMA7110 functional description external interrupts 0 and 1 the has two external interrupt sources ext_int0 on pp9 and ext_int1 on pp7. as in the cpu8051 the control bits and interrupt flags can be found in the tcon register (please refer to table 44 on page 92 ). when enabled by setting ie.0 [ex0] for external interrupt 0 (resp. ie.2 [ex1] for external interrupt 1) interrupts can be generated from pp9 (resp. pp7). the external interrupts 0 and 1 can be programmed to be level-activated or negative- transition activated by clearing or setting bit tcon.0 [it0], respectively tcon.2 [it1]. if bit itx = 0, the corresponding external interrupt is triggered by a detected low level at the pin. if itx = 1, the corresponding external interrupt is negative edge-triggered. in this mode, if successive samples of the pin show a high in one cycle and a low in the next cycle, interrupt request flag iex in tcon is set. flag bit iex=1 then requests the interrupt. if the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. each of the external interrupts has its own interrupt vector. timer interrupts all four timers on the can be used as interrupt sources. while timer 0 and timer 1 are fully compatible to the original cpu8051 (for a description please refer to ?timer/counter interrupts? on page 96 ), timer 2 and timer 3 interrupts are treated as extended interrupts. i2c interface interrupts the data interface transfer on the i2c module can be controlled via interrupts. this module has a separte interrupt vector (vector address 23 h ) where the pc is automatically set whenever one of the interrupt flags active and unmasked. in test- , debug- and programming mode the i2c interface handling is done by polling. spi interface interrupts the data transfer on the spi interface can be controlled via interrups. this module has a separte interrupt vector (vector address 2b h ) where the pc is automatically set whenever one of the interrupt flags is active and unmasked. lf receiver interrupts targetdatasheet.book page 75 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 76 v0.9, 2008-04-28 while the main target for lf receiver operation is waking up the device, it is also possible to receive data via the lf interface in run mode. the wake-up flags are used as interrupt event flags and wake-up mask bits are used as interrupt mask bits as well. rf encoder interrupts note: it is recommended to keep the cpu in idle state during rf transmission whenever possible. nevertheless, it is possible to coordinate the data transfer interrupt driven. therefore, two interrupt sources are available for rf transmission: interrupt source flags: ? rfs.0 [rfbf] rf encoder buffer full ? rfs.1 [rfse] rf encoder shift register empty table 30 sfr address a8 h : ie-interrupt enable register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ea eid espi ei2c et1 ex1 et0 ex0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 ea global interrupt enable bit eid enable extended interrupts (timer2/3, lf receiver, rf encoder) espi enable interrupts from the spi interface ei2c enable interrupts from i2c interface et1 enable interrupts from timer 1 ex1 enable interruots from external interrupt 1 (pp7) et0 enable interrupts from timer 0 ex0 enable interrupts from external interrupt 0 (pp9) targetdatasheet.book page 76 monday, april 28, 2008 11:16 am
preliminary data sheet 77 v0.9, 2008-04-28 PMA7110 functional description table 31 sfr address b8 h : ip-interrupt priority register table 32 sfr address 8f h : irqfr-interrupt request flag register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. pid pspi pi2c pt1 px1 pt0 px0 r 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 pid priority level for extended interrupts (timer2/3, lf receiver, rf encoder) 1: high priority interrupt 0: low priority interrupt pspi priority level for interrupts from the spi interface pi2c priority level for interrupts from i2c interface pt1 priority level for interrupts from timer 1 px1 priority level for interruots from external interrupt 1 (pp7) pt0 priority level for interrupts from timer 0 px0 priority level for interrupts from external interrupt 0 (pp9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. irqfmc irflf irqft3 irqft2 r 0/0 r 0/0 r 0/0 r 0/0 rc 0/0 rc 0/0 r 0/0 r 0/0 irqfmc interrupt request flag rf encoder irqflf interrupt request flag lf receiver irqft3 interrupt request flag timer 3 irqft2 interrupt request flag timer 2 targetdatasheet.book page 77 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 78 v0.9, 2008-04-28 2.5.9 rf 315/434/868/915 mhz fsk/ask transmitter the rf transmitter consists of a pll frequency synthesizer that is contained fully on chip, a lock detector and a power amplifier. figure 15 rf transmitter block diagram the rf-transmitter can be configured for the 315/434/868/915 mhz ism-band frequencies by setting sfr bits rftx.3-2[ismb1-0] and choosing the proper crystal. manchester/biphase/nrz coded data with a bit rate up to 20kbit/s (40kchips/s) can be transmitted using ask or fsk modulation. pll vco pa loop- filter cp phase detector crystal 315 mhz 434 mhz 868 mhz 915 mhz 1890mhz 1736mhz 1736mhz 1830mhz divider 2 divider 1/2/3 divider 4 divider 6/3/2 divider 2 pll lock detector (used by rom library function) sfr rftx.3-2 ismb1-0 0 - 315 mhz 1 - 434 mhz 2 - 868 mhz 3 - 915 mhz sfr rftx.1 -0 pa op1 -0 sfr r fc.0 enpa fsk-mod fsk- transmit data ask- transmit data manchester/ biphase encoder sfr rfs sfr rfenc sfr rfd sfr rftx.6 itxd sfr rftx.5 askfsk l o g i c transmit data sfr r fc en fsyn buffer cdcc dcc 00 - 44% 01 - 39% 10 - 34% 11 - 27% targetdatasheet.book page 78 monday, april 28, 2008 11:16 am
preliminary data sheet 79 v0.9, 2008-04-28 PMA7110 functional description table 33 sfr address ae h : rftx - rf transmitter control register 1 the pll synthesizer and the power amplifier can be enabled seperately by using the sfr rfc control register. the power amplifier should be switched on with a delay of at least 100s after enabling the frequency synthesizer. this delay is needed for pll locking. table 34 sfr address ee h : rfc - rf transmitter control register 2.5.9.1 phase locked loop pll the pll consists of an on-chip vco, an asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and an internal loop filter. (see table 118 "sfr address de h : rfvco -rf frequency synthesizer vco config" on page 151 ) the pll can be enabled manually by setting sfr bit rfc.1[enfsyn]. the pll lock frequency is determined by the used crystal (see table 25 "formulas for crystal selection dependent of rf- bands" on page 71 ) and the appropriate configuration in the sfr bits rftx.3-2[ismb1-0]. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xcapsh invtxdat askfsk n.u. ismb1 ismb0 paop1 paop0 w 0/0 w u/0 w u/0 0/0 w u/0 w u/1 w u/1 w u/1 xcapsh enable xcap short invtxdat invert tx data askfsk tx ask/fsk modulation select 1: ask 0: fsk ismb1-0 rf frequency select 1xb: 868mhz/915mhz 01b: 434mhz 00b: 315mhz paop1-0 rf power amplifier output power select 11b: 10dbm 10b: 8dbm 01b: 8dbm 00b: 5dbm bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. enfsyn enpa 0/0 0/0 0/0 0/0 0/0 0/0 rw 0/0 rw 0/0 enfsyn enable rf frequency synthesizer enpa enable rf power amplifier targetdatasheet.book page 79 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 80 v0.9, 2008-04-28 2.5.9.2 power amplifier pa the highly efficient power amplifier is enabled automatically if a byte is transmitted (rfs.1 [rfse] is set to ?0?) and if tx data are not output on pin pp2 (cfg1.4 [rftxpen]). alternatively the power amplifier is enabled immediately by using rfc.0 [enpa]. the nominal transmit power levels are +5/8/10dbm into 50 ohm load at a supply voltage of 3.0v. the power amplifier operating point must be optimized to the output power +5/8/10dbm regarding current consumption by properly setting the rftx.1-0 [paop1-0], rffspll.3-2 [dcc1-0] and using an optimal sized matching circuit. the power amplifier should be enabled at least 100 s after enabling the rf frequency synthesizer because of the pll lock in time. 2.5.9.3 ask modulator ask modulation is done by turning on and off the power amplifier dependent on the baseband data to be transmitted (on/off-keying) by using rfenc.3 [txdd] or the manchester/biphase encoder (see also ?manchester/biphase encoder with bit rate generator? on page 81 ). about fsk modulation please see ?crystal oscillator? on page 71 . 2.5.9.4 voltage controlled oscillator (vco) the vco is using on-chip inductors and varactors for tuning and has a nominal center frequency of 1750mhz. the tuning range vco is split up into 16 frequency ranges. figure 16 vco tuning characteristic loop filter tuning voltage [ v] vco-frequency [mhz] 0000 1111 1110 0011 0001 1700 1900 sfr rfvco vcof3 vcof2 vcof1 vcof0 0100 targetdatasheet.book page 80 monday, april 28, 2008 11:16 am
preliminary data sheet 81 v0.9, 2008-04-28 PMA7110 functional description automatically by the operating system after power up or a system reset by using the pll lock detector and the pll lock detection routine. additionally, the vco is always recalibrated by firmware if the crystal oscillator is selected as clock source by setting cfg0.0 [clksel]. table 118 "sfr address de h : rfvco -rf frequency synthesizer vco config" on page 151 additionally, the pll lock detector for vco tuning curve selection may be used by the user program code before rf data transmission. the pll lock detection routine can be called by the user program for that reason. table 119 "sfr address d4h: adcdl - adc result register (low byte)" on page 151 a rom library function is available which selects the tuning curve automatically dependent on environmental conditions (temperature, v bat ). note: recalibration of the tuning curve is typically necessary when the supply voltage changes by more than 800mv or the temperature changes by more than 70 degrees. for details on the rom library functions please refer to [1] ?reference sfr registers? on page 144 . 2.5.9.5 manchester/biphase encoder with bit rate generator the interface between the cpu and the rf transmitter offers a manchester/biphase encoder. the encoding bitrate can be set with timer 3 (see ?timer unit (timer 0, timer 1, timer 2, timer 3)? on page 90 ) and may be programmed within a broad range. figure 17 manchester/biphase encoder baudrate generator 8-bit data value sfr rfd 8-bi t sh iftre g iste r shiftr e g em pty rfse buffer full rfbf sfr rfs encoder sfr rfenc raw data modulation clock quiescent state txdd & ms b transmit data timer3 overflow 3-bit data length rfdlen 3-bit data mode rfmode[2-0] po w e r en a b le targetdatasheet.book page 81 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 82 v0.9, 2008-04-28 the manchester/biphase encoder automatically enables the power amplifier when a new databyte is written to sfr rfd. the power amplifier is disabled after transmitting the last data bit automatically as well. it is also possible to send data with a user-defined encoding scheme, e.g. for sending a preamble. this can be achieved by using chipmode (sfr bits rfenc.2-0[rfmode2-0] = 101b). the chipmode sends each bit without encoding, but twice the data rate. the encoding selection can be changed everytime before a data byte is written to the sfr rfd by adjusting sfr bits rfenc.2-0[rfmode2-0]. the sfr bit rfenc.3[txdd] defines the data value assigned to manchester/biphase encoder output when no data is available in the sfr rfd. note: if sfr bit rfc.1-0[enfsyn enpa] is set the sfr bit rfenc.3[txdd] controls directly the transmitter state. by using this feature the user has full control of the transmit data without any restrictions in timing or protocol. table 35 sfr address e7 h : rfenc - rf encoder tx control register by writing a databyte to the sfr rfd the data transmission is invoked automatically. per default the transmission takes place byte-aligned. if less than 8 bits should be transmitted, sfr bits rfenc.7-5[rfdlen2-0] can be set to determine the number of bits that should be transmitted. table 36 sfr address 8e h : rfd - rf encoder tx data register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rfdlen2 rfdlen1 rfdlen0 rfmask txdd rfmode2 rfmode1 rfmode0 rw 1/1 rw 1/1 rw 1/1 rw 0/0 rw 0/0 rw =0/0 rw 0/0 rw 0/0 rfdlen2-0 rf data length - number of bits to be transmitted from sfr rfd txdd transmit data if sfr bit rfc.1-0 [enfsyn enpa] is set. rfmask rf interrupt mask flag rfmode2-0 rf encoder mode 000b: manchester: 0? is encoded as low-to-high, ?1? as high-to-low transition 001b: inverted manchester: ?0? is encoded as high-to-low, ?1? as low-to-high transition 010b: differential manchester ?0? is encoded as transition 011b: biphase: ?0? is encoded transition 100b: biphase: ?1? is encoded transition 101b: data bits are interpreted as chips 110b: reserved 111b: reserved sfr (abbr): addr access default value register rfd 8e h w u/00 h rf encoder data register targetdatasheet.book page 82 monday, april 28, 2008 11:16 am
preliminary data sheet 83 v0.9, 2008-04-28 PMA7110 functional description the following figure shows the different timing diagrams for the different encoding schemes: figure 18 diagram of the different rf encoder modes. timer 3 (see ?timer unit (timer 0, timer 1, timer 2, timer 3)? on page 90 ) provides the bitrate clock and has to be set according to the desired bitrate. the bitrate timer value can be calculated with the following formula: this timervalue has to be written to the timer registers (see table 43 "sfr address 8ah--8dh and cah--cdh: timer registers" on page 92 ). data clock manchester inverted manchester differential manchester biphase-0 biphase-1 10100110 sfr rfd clock chip 10100110 encoder- mode (manchester/biphase) chip- mode time start of data transmission transmission finished in chip-mode transmission finished in encoder-mode timervalue f timerclocksource hz [] 8 bitrate 1 s -- - ? ------------------------------------------------- 1 ? = targetdatasheet.book page 83 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 84 v0.9, 2008-04-28 the sfr rfs represents the status of the rf encoder. after writing a databyte to sfr rfd, the sfr bit rfs.0[rfbf] is set. it is cleared automatically when the databyte in sfr rfd is transferred to the shiftregister. the application should poll sfr bit rfs.0[rfbf] to determine when the data is transferred to the shiftregister and sfr rfd can take the next data byte for processing. it is necessary to provide the transmitter with a continous data stream to prevent the receiver from losing synchronization. sfr bit rfs.1[rfse] is set if there is no data available in the shiftregister and cleared if the shiftregister contains data that has to be transmitted. note: this flag is used internally to switch on/off the power amplifier, thus is can be used by the application to determine if the power amplifier is currently active (sfr bit rfs.1[rfse] == ?0?) or not active (sfr bit rfs.1[rfse] == ?1?). table 37 sfr address e6 h : rfs - rf encoder status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. rfse rfbf 0/0 0/0 0/0 0/0 0/0 0/0 r 1/1 r 0/0 rfse rf encoder shift-register empty automatically set by hardware if no further bits are available in shift register. rfbf rf encoder buffer full automatically set by hardware on write access to rfd register or cleared if data in register rfd is transferred to shift register respectively. targetdatasheet.book page 84 monday, april 28, 2008 11:16 am
preliminary data sheet 85 v0.9, 2008-04-28 PMA7110 functional description 2.5.10 lf receiver the lf receiver is used for data transmission to the PMA7110, as well as for waking up the PMA7110 from power down state. it can generate a wakeup directly by the carrier detector if the carrier amplitude is above a preset threshold, or it can decode the received data and not wake up the microcontoller until a predefined sync match pattern or wakeup pattern is detected in the data stream. data recovery using a synchronizer and a decoder is available for manchester and biphase coded data. the synchronizer can also handle manchester/biphase code violations. any other coding scheme can be handled by the microcontroller on chip level, thus no limitations on data coding schemes apply. a lf on/off timer is implemented to generate periodical on/off switching of the lf receiver in power down state. this can be done to reduce the current consumption. targetdatasheet.book page 85 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 86 v0.9, 2008-04-28 2.5.11 16bit crc (cyclic redundancy check) generator/checker figure 19 crc (cyclic redundancy check) generator/checker crc is a powerful method to detect errors in datapackets that have been transmitted over a distorted connection. the crc generator/checker divides each byte of a datapacket that is transmitted/received, by a polynomial, leaving the remainder, which represents the checksum. the crc-generator/checker is using the 16bit ccitt polynomial 1021 h (x 16 +x 12 +x 5 +1). the 16 bit start value is determined by sfr crc0 and sfr crc1. the crc generator/checker can process 8 bit parallel and/or serial data. table 38 crc data & result register sfr (abbr) addr access default value register crcd aa h rw 00 h crc data register crc0 ac h rw 00 h crc result register 0 low byte crc1 ad h rw 00 h crc result register 1 high byte crc shiftregister/logic crc-data 8-bit sfr crcc crcsd msb sfr crcd data strobe crc-ccitt sfr crcr1 sfr crcr0 crcss crc-result <15:8> crc-result <7:0> polynomial = 0x1021 sfr crcs crcvalid targetdatasheet.book page 86 monday, april 28, 2008 11:16 am
preliminary data sheet 87 v0.9, 2008-04-28 PMA7110 functional description table 39 sfr address a9 h : crcc - crc control register byte aligned crc generation crc generation is done executing the following steps: ? the crc shiftregister has to be initialized e.g. with ?1?s by writing ff h to both sfr crc0 and sfr crc1. ? the databytes which should be checked by the crc checker have to be shifted one after the other into the sfr crcd. the process of crc generation is automatically invoked when data bytes are written to the sfr crcd. ? the resulting checksum value is available in the crc result register sfr crc0 and sfr crc1 after processing the last data byte. byte aligned crc checking crc checking is done in the following steps: ? the crc shiftregister has to be initialized e.g. with ?1?s by writing ff h to both sfr crc0 and sfr crc1. ? the databytes which should be checked by the crc checker have to be shifted serially (one after the other) into the sfr crcd. it is important that the order (msb- lsb) is the same as it was during the crc generation. the process of crc checking is automatically invoked when data bytes are written to the sfr crcd. ? write the 16 bit crc-value to the sfr crcd beginning with the high byte after processing all user-data. ? the sfr bit crcc.1[crcvalid] indicates the correctness of the crc calculation after processing the last data byte. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. crcsd crcss n.u. n.u. n.u. crcvalid n.u. 0/0 rw 0/0 w 0/0 0/0 0/0 0/0 r 1/1 0/0 crcsd crc serial data crcss crc serial data strobe use crcss to serial strobe data bit crcsd into crc encoding/decoding procedure. crcvalid crc valid is set by hardware on vaild crc results, that means all crc-bits are 0. targetdatasheet.book page 87 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 88 v0.9, 2008-04-28 serial bitstream crc generation/checking the crc generator/checker features an additional serial mechanism to perform crc generation and checking of non byte-aligned data streams. in this case sfr bit crcc.5[crcss] and sfr bit crcc.6[crcsd] are used instead of sfr crcd. the data stream is written bit by bit into sfr bit crcc.6[crcsd]. each bit is processed by forcing the flag sfr bit crcc.5[crcss]. the following figure shows an example for the usage of sfr bit crcc.5[crcss] and sfr bit crcc.6[crcsd]. figure 20 example for serial crc generation/checking note: the serial and byte-aligned generation/checking mechanism is interchangeable within the same generation/checking process. e.g. if a data packet consists of 18 bits , then 16 bits can be processed byte-aligned via sfr crcd and the two remaining bits can be processed bit-aligned by using sfr bit crcc.5[crcss] and sfr bit crcc.6[crcsd]. crcc.6 [crcsd] data to be encoded 0 1 1 0 0 0 1 0 1 1 1 0 0 crcc.5 [crcss] targetdatasheet.book page 88 monday, april 28, 2008 11:16 am
preliminary data sheet 89 v0.9, 2008-04-28 PMA7110 functional description 2.5.12 pseudo random number generator for many applications a pseudo random number generator is needed, e.g. to vary the interval period between transmissions. for this purpose a maximum length linear feedback shift register (mlfsr) is available as a hardware unit. table 40 sfr address ab h : sfr rngd - random number generator data a user-defined start value (except 00 h ) can be written to sfr rngd. the default value after startup is 55 h . the generation of a new random number is initiated by setting sfr bit cfg1.5[rngen]. after the random number is generated, sfr bit cfg1.5[rngen] is reset automatically and the value is available in sfr rngd. sfr (abbr) addr access default value register rngd ab h rw u/55 h random number generator data register targetdatasheet.book page 89 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 90 v0.9, 2008-04-28 2.5.13 timer unit (timer 0, timer 1, timer 2, timer 3) the PMA7110 comprises four independent 16 bit timers. timer 0/1 operate as up- counters, timer 2/3 operate as down-counters. timer / counter 0 and 1 are fully compatible with timer / counter 0 and 1 of the standard 8051 and can be used in the same four operating modes: ? mode 0: 8-bit timer/counter with a divide-by-32 prescaler ? mode 1: 16-bit timer/counter ? mode 2: 8-bit timer/counter with 8-bit auto-reload ? mode 3: timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer/counter 1 in this mode holds its count. the effect is the same as setting tr1 = 0. the external inputs pp1 and pp9 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. each timer consists of two 8-bit registers (th0 and tl0 for timer/counter 0, th1 and tl1 for timer/counter 1) which may be combined to one timer configuration depending on the mode that is established. the functions of the timers are controlled by two special function registers tcon and tmod. in the following descriptions the symbols th0 and tl0 are used to specify the high-byte and the low-byte of timer 0 (th1 and tl1 for timer 1, respectively). the operating modes are described and shown for timer 0. if not explicity noted, this applies also to timer 1. 2.5.13.1 basic timer configuration timer 0 -timer 3 comprise four fully programmable 16-bit timers, which can be used for time measurements as well as generating time delays. the clock source is selectable in order to enlarge the timer runtime. sfr tmod and sfr tmod2 are used to select the clock source and the desired timer mode. table 41 sfr address 89 h : tmod - timer mode register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 t1gate timer 1 gate control bit (gating input: pp8) t1c/t timer 1 counter / not timer (count input: pp9) t1m1-0 timer 1 mode 00b: mode 0. 8-bit timer with a divided-by-32 prescaler 01b: mode 1.16-bit timer 10b: mode 2. 8-bit timer with 8-bit auto-reload 11b: mode 3. timer 1 hold its count. the effect is the same like setting tr1=0 t0gate timer 0 gate control bit (gating input: pp0) targetdatasheet.book page 90 monday, april 28, 2008 11:16 am
preliminary data sheet 91 v0.9, 2008-04-28 PMA7110 functional description table 42 sfr address c9 h : tmod2 - timer mode register 2 (timer 2/3) the timer registers described in table 43 "sfr address 8ah--8dh and cah--cdh: timer registers" on page 92 are used as start values and - once the timer is started - hold the actual counter values and can be read by the application at any time. note: the purpose of these registers depends on the selected timer mode. t0c/t timer 0 counter / not timer (count input: pp1) t0m1-0 timer 0 mode 00b: mode 0. 8-bit timer with a divided-by-32 prescaler 01b: mode 1.16-bit timer 10b: mode 2. 8-bit timer with 8-bit auto-reload 11b: mode 3. two 8-bit timers. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t3clk1 t3clk0 t2clk1 t2clk0 n.u. tm2 tm1 tm0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 0/0 rw 0/0 rw 0/0 rw 0/0 t3clk1-0 timer 3 clock source select 00b: undivided systemclock (see figure "PMA7110 internal clock divider" on page 71 ) 01b: systemclock divided by 8 (see figure "PMA7110 internal clock divider" on page 71 ) 10b: 2 khz lp rc oscillator clock 11b: pp2 event count (rising edge) t2clk1-0 timer 2 clock source select 00b: undivided systemclock (see figure "PMA7110 internal clock divider" on page 71 ) 01b: systemclock divided by 8 (see figure "PMA7110 internal clock divider" on page 71 ) 10b: 2 khz lp rc oscillator clock 11b: timer 3 overflow event count tm2-0 timer mode 000b: mode 0 001b: mode 1 010b: mode 2 011b: mode 3 100b: mode 4 101b: mode 5 110b: not used 111b: mode 7 targetdatasheet.book page 91 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 92 v0.9, 2008-04-28 table 43 sfr address 8a h --8d h and ca h --cd h : timer registers sfr tcon and sfr tcon2 are used for starting and stopping timers and for status indication of all timers. note: the purpose of this bits depends on the selected timer mode. table 44 sfr address 88 h : tcon - timer control register setting the sfr bit tcon.4[tr0] (respectively sfr bit tcon.6[tr1]) starts timer 0 (resp. timer 1). it counts using the selected clock (see sfr tmod) until the timer is elapsed. sfr bit tcon.5[tf0] (resp. sfr bit tcon.7[tf1] is set. if the selected timer mode used timer reload, then the timer is automatically reloaded and restarted. if the selected timer mode doesn?t use timer reload, the timer is stopped and sfr bit tcon.4[tr0] (resp. sfr bit tcon.6[tr1]) is cleared. sfr (abbr) addr access default value register th0 8c h rw 00 h /00 h timer 0 register upper byte tl0 8a h rw 00 h /00 h timer 0 register lower byte th1 8d h rw 00 h /00 h timer 1 register upper byte tl1 8b h rw 00 h /00 h timer 1 register lower byte th2 cd h rw 00 h /00 h timer 2 register upper byte tl2 cc h rw 00 h /00 h timer 2 register lower byte th3 cb h rw 00 h /00 h timer 3 register upper byte tl3 ca h rw 00 h /00 h timer 3 register lower byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 tf1 timer 1 overflow flag tr1 timer 1 run control bit tf0 timer 0 overflow flag tr0 timer 0 run control bit ie1 interrupt 1 edge flag it1 interrupt 1 type control bit ie0 interrupt 0 edge flag it0 interrupt 0 type control bit targetdatasheet.book page 92 monday, april 28, 2008 11:16 am
preliminary data sheet 93 v0.9, 2008-04-28 PMA7110 functional description table 45 sfr address c8 h : tcon2 - timer control register 2 setting the sfr bit tcon2.0[t2run] (respectively sfr bit tcon2.4[t3run]) starts timer 3 (resp. timer 2). it counts using the selected clock (see sfr tmod) until the timer is elapsed. sfr bit tcon2.1[t2full] (resp. sfr bit tcon2.5[t3full] is set. if the selected timer mode used timer reload, then the timer is automatically reloaded and restarted. if the selected timer mode doesn?t use timer reload, the timer is stopped and sfr bit tcon2.0[t2run] (resp. sfr bit tcon2.4[t3run]) is cleared. 2.5.13.2 general operation description timer 0 and timer 1 mode 0 when putting timer/counter 0 (resp. timer/counter 1) into mode 0 the timer is configured as an 8-bit timer/counter with a divide-by-32 prescaler. figure 21 "timer/counter 0, mode 0, 13-bit timer/counter." on page 94 shows the mode 0 operation. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer overflow flag tcon.5 [tf0] (resp. tcon.7 [tf1]). the overflow flag tcon.5 [tf0] (resp. tcon.7 [tf1]) can then be used to request an interrupt. the counted input is enabled to the timer when tcon.4 [tr0] = 1 and either tmod.3 [t0gate] = 0 or int0 = 1 (setting t0gate = 1 allows the timer to be controlled by external input pp1 (resp. pp9), to facilitate pulse width measurements). the 13-bit register consists of all 8 bits of th0 (resp. th1) and the lower 5 bits of tl0 (resp tl1). the upper 3 bits of tl0 (resp. tl1) are indeterminate and should be ignored. setting the run flag tcon.4 [tr0] (resp. tcon.6 [tr1]) does not clear the registers. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t3mask n.u. t3full t3run t2mask n.u. t2full t2run rw 0/0 0/0 rw 0/0 rw 0/0 rw 0/0 0/0 rw 0/0 rw 0/0 t3mask timer 3 interrupt mask bit. when set to zero the interrupt from timer 3 is disabled t3full timer 3 full bit t3run timer 3 run bit t2mask timer 2 interrupt mask bit. when set to zero the interrupt from timer 2 is disabled t2full timer 2 full bit t2run timer 2 run bit targetdatasheet.book page 93 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 94 v0.9, 2008-04-28 figure 21 timer/counter 0, mode 0, 13-bit timer/counter. figure 22 timer/counter 1, mode 0, 13-bit timer/counter mode 1 mode 1 is equal to mode 0 with the difference that the timer register is running with all 16 bits. mode 2 mode 2 configures the timer registers as an 8-bit counter in tl0 (resp. tl1) with automatic reload, as shown in figure 23 "timer/counter 0, mode 2: 8-bit timer/counter with auto-reload" on page 95 . overflow from tl0 (resp. tl1) not only sets tcon.5 [tf0] (resp. tcon.7 [tf1]) , but also reloads tl0 (resp. tl1) with the timer01_mode0.vsd osc tl0 (5 bits) th0 (8 bits) tcon.5 [tf0] interrupt timer 0 & tcon4.[tr0] 1 tmod.2[t0c/t] t0gate/pp0 t0count/pp1 tmod3.[t0gate] 1 1 _ > - :6 0 & ie.1[et0] ie.7[ea] timer01_mode0.vsd osc tcon.7 [tf1] interrupt timer 1 & tcon6.[tr1] 1 tmod.6[t1c/t] t1gate/pp8 t1count/pp9 tmod7.[t1gate] 1 1 _ > - :6 0 tl1 (5 bits) th1 (8 bits) & ie.3[et1] ie.7[ea] targetdatasheet.book page 94 monday, april 28, 2008 11:16 am
preliminary data sheet 95 v0.9, 2008-04-28 PMA7110 functional description contents of th0 (resp. th1) , which is preset by software. the reload leaves th0 (resp. th1) unchanged. figure 23 timer/counter 0, mode 2: 8- bit timer/counter with auto-reload mode 3 mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply holds its count. the effect is the same as setting tcon.6 [tr1]=0. timer 0 establishes tl0 and th0 as two separate counters ( figure 24 "timer/counter 0, mode 3: two 8-bit timers/counters" on page 96 ). tl0 uses the timer 0 control bits: tmod.2 [t0c/t], tmod.3 [t0gate], tcon.4 [tr0], tcon.5 [tf0] and the pin status of pp0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tcon.6 [tr1] and tcon.7 [tf1] from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or in fact, in any application not requiring an interrupt from timer 1 itself. timer01_mode2.vsd tl0 (8 bits) th0 (8 bits) tcon.5 [tf0] reload osc & tcon4.[tr0] 1 tmod.2[t0c/t] t0gate/pp0 t0count/pp1 tmod3.[t0gate] 1 1 _ > - :6 0 interrupt timer 0 & ie.1[et0] ie.7[ea] targetdatasheet.book page 95 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 96 v0.9, 2008-04-28 figure 24 timer/counter 0, mode 3: two 8-bit timers/counters interrupt support this module supports interrupt generation on overrun of timer/counter 0 as well as timer/counter 1. additional to these timer/counter interrupts, two external interrupts are handled by this unit, too (ref. to standard 8051). when an interrupt event occurs in idle state, the device starts operation immediately and the pc is set to the appropriate interrupt vector. timer/counter interrupts on overrun of the upcounting timer/counter from all ?1? to all ?0? the flag tcon.5 [tf0] or tcon.7 [tf1] is set by hardware. these flags acts as interrupt request flags: a ?1? indicates a pending interrupt request. these flags are cleared by hardware as on standard 8051 when the corresponding interrupt vector has been fetched by the cpu. external interrupts 0 and 1 as on the standard 8051, the interrupt control bits for the external interrupts 0 and 1 are located in the tcon register. for a detailed description of the external interrupts please refer to ?interrupt sources on the ? on page 74 . timer01_mode3.vsd tcon.5 [tf0] interrupt timer 0 tcon.7 [tf1] interrupt timer 1 tcon.6[tr1] osc & tcon4.[tr0] 1 tmod.2[t0c/t] t0gate/pp0 t0count/pp1 tmod3.[t0gate] 1 1 _ > - :6 0 & ie.3[et1] ie.7[ea] & ie.1[et0] ie.7[ea] tl0 (8 bits) th0 (8 bits) targetdatasheet.book page 96 monday, april 28, 2008 11:16 am
preliminary data sheet 97 v0.9, 2008-04-28 PMA7110 functional description 2.5.13.3 timer modes for timer 2 and timer 3 timer mode 0 comprises: ? 16 bit timer with reload the timer unit is configured as a 16 bit reloadable timer. sfr tl2 and sfr th2 hold the start value. if sfr bit tcon2.0[t0run] is set, the timer starts down counting. sfr bit tcon2.1[t0full] is set when the timer is elapsed (underflow from 0 to 0xff). the timer value is reloaded from sfr tl3 and sfr th3 and the timer is restarted automatically. sfr bit tcon2.1[t0full] has to be reset by software. it is not cleared on read-access. note: in this mode, both sfr bit tcon2.4[t1run] and sfr bit tcon2.5[t1full] are not used. figure 25 timer mode 0 t2run t3run timer 2 timer 2 reload tl2 t2full t3full reload th2 tl3 th3 interrupt timer 2 & t2mask ie.6[eid] ie.7[ea] targetdatasheet.book page 97 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 98 v0.9, 2008-04-28 timer mode 1 comprises: ? 16 bit timer without reload ? 8 bit timer with reload and bitrate strobe signal for rf transmitter timer 2 operates as 16 bit timer with start value in sfr tl2 and sfr th2, timer run bit sfr bit tcon2.0[t0run] and timer elapses indicator sfr bit tcon2.1[t0full]. if the timer elapses, it stops, sets sfr bit tcon2.1[t0full] and resets the timer run bit sfr bit tcon2.0[t0run]. timer 3 sets up a reloadable 8 bit timer holding the startup value in sfr tl3, timer reload value in sfr th3, timer run bit in sfr bit tcon2.4[t1run] and timer elapses indicator in sfr bit tcon2.5[t1full]. figure 26 timer mode 1 t3mask ie.6[eid] ie.7[ea] t2run t3run timer 2 timer 3 tl2 t3full th2 tl3 th3 timer 3 reload reload baudrate strobe interrupt timer 2 & t2mask ie.6[eid] t2full interrupt timer 3 & ie.7[ea] targetdatasheet.book page 98 monday, april 28, 2008 11:16 am
preliminary data sheet 99 v0.9, 2008-04-28 PMA7110 functional description timer mode 2 comprises: ? 8 bit timer with reload ? 8 bit timer with reload and bitrate strobe signal for rf transmitter timer 2 sets up a reloadable 8 bit timer holding the start value sfr tl0, timer reload value sfr th0, timer run bit sfr bit tcon2.0[t0run] and timer elapsed indicator sfr bit tcon2.1[t0full]. timer 3 sets up a reloadable 8 bit timer holding the start value sfr tl1, timer reload value sfr th1, timer run bit sfr bit tcon2.4[t1run] and timer elapsed indicator sfr bit tcon2.5[t1full] . figure 27 timer mode 2 t2run t3run timer 3 tl2 th2 tl3 th3 timer 3 reload reload baudrate strobe timer 2 timer 2 reload reload interrupt timer 2 & t2mask ie.6[eid] t2full ie.7[ea] t3mask ie.6[eid] ie.7[ea] t3full interrupt timer 3 & targetdatasheet.book page 99 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 100 v0.9, 2008-04-28 timer mode 3 comprises: ? 8 bit timer without reload (1) ? 8 bit timer without reload (2) ? 8 bit timer with reload and bitrate strobe signal for rf transmitter timer 2 (1) utilizes sfr tl0 as starting value and t0full as timer elapsed flag. setting sfr bit tcon2.0[t0run] starts the timer, and sfr bit tcon2.1[t0full] is set when the timer is elapsed. sfr bit tcon2.0[t0run] is reset automatically if the timer elapses. timer 3 (2) utilizes sfr th0 as starting value and sfr bit tcon2.5[t1full] as timer elapsed flag. setting sfr bit tcon2.4[t1run] starts the timer, and sfr bit tcon2.5[t1full] is set when the timer is elapsed. sfr bit tcon2.4[t1run] is reset automatically if the timer elapses. timer 3 operates exclusive as 8-bit bitrate timer for manchester coding. therefore the timer needs neither a run nor an elapsed bit. it is started automatically when the timer mode is set. figure 28 timer mode 3 t2run t3run timer 3 tl2 th2 tl3 th3 timer 3 reload reload baudrate strobe timer 2 (1) timer 2 (2) t3mask ie.6[eid] ie.7[ea] t3full interrupt timer 3 & interrupt timer 2 & t2mask ie.6[eid] t2full ie.7[ea] targetdatasheet.book page 100 monday, april 28, 2008 11:16 am
preliminary data sheet 101 v0.9, 2008-04-28 PMA7110 functional description timer mode 4 comprises: ? 16 bit timer with reload and bitrate strobe signal for rf transmitter the timer unit is configured as a 16 bit reloadable timer. sfr tl1 and sfr th1 hold the start value. if sfr bit tcon2.4[t1run] is set, the timer starts counting. sfr bit tcon2.5[t1full] is set when the timer is elapsed. the timer value is reloaded from sfr tl0 and sfr th0 and the timer is restarted automatically. sfr bit tcon2.5[t1full] has to be reset by software. it is not cleared on read-access. note: in this mode both sfr bit tcon2.0[t0run] and sfr bit tcon2.1[t0full] are not used. figure 29 timer mode 4 t2run t3run timer 3 reload timer 3 tl2 t2full reload th2 tl3 th3 t3mask ie.6[eid] ie.7[ea] t3full interrupt timer 3 & targetdatasheet.book page 101 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 102 v0.9, 2008-04-28 timer mode 5 comprises: ? 8 bit timer with reload ? 16 bit timer without reload and bitrate strop signal for rf transmitter sfr bit tcon2.0[t0run] starts the timer, and sfr bit tcon2.1[t0full] timer 2 sets up a reloadable 8 bit timer holding the start value in sfr tl0, timer reload value in sfr th0, timer run bit sfr bit tcon2.0[t0run] and timer elapsed indicator in sfr bit tcon2.1[t0full]. timer 3 operates as a 16 bit timer with the start value in sfr tl1 and sfr th1, timer run bit sfr bit tcon2.4[t1run] and timer elapsed indicator sfr bit tcon2.5[t1full]. if the timer elapses, the timer stops sfr bit tcon2.5[t1full] is set and the timer run bit sfr bit tcon2.4[t1run] is reset. figure 30 timer mode 5 t2run t3run timer 2 timer 3 tl2 th2 tl3 th3 reload timer 2 reload t3mask ie.6[eid] ie.7[ea] t3full interrupt timer 3 & interrupt timer 2 & t2mask ie.6[eid] t2full ie.7[ea] targetdatasheet.book page 102 monday, april 28, 2008 11:16 am
preliminary data sheet 103 v0.9, 2008-04-28 PMA7110 functional description timer mode 6 comprises: ? 16 bit timer without reload ? 16 bit timer without reload and bitrate strobe signal for rf transmitter timer 2 operates as a 16 bit timer with the start value in sfr tl0 and sfr th0, timer run bit sfr bit tcon2.0[t0run] and timer elapsed indicator sfr bit tcon2.1[t0full]. if the timer is elapsed the timer is stopped, sfr bit tcon2.1[t0full] is set and the timer run bit sfr bit tcon2.0[t0run] is reset. timer 3 operates as a 16 bit timer with the start value in sfr tl1 and sfr th1, timer run bit sfr bit tcon2.4[t1run] and timer elapsed indicator sfr bit tcon2.5[t1full]. if the timer elapses, the timer stops, sfr bit tcon2.5[t1full] is set and the timer run bit sfr bit tcon2.4[t1run] is reset. figure 31 timer mode 6 t2run t3run timer 2 reload timer 3 tl2 th2 tl3 th3 interrupt timer 2 & t2mask ie.6[eid] t2full ie.7[ea] ie.6[eid] ie.7[ea] t3full interrupt timer 3 & t3mask targetdatasheet.book page 103 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 104 v0.9, 2008-04-28 timer mode 7 comprises: ? 16 bit timer for interval timer calibration ? 8 bit timer with reload and bitrate strobe signal for rf transmitter timer 2 operates as 16 bit clock counter during one 2 khz rc lp oscillator period with the counting value provided in sfr tl0 and sfr th0, a timer run bit sfr bit tcon2.0[t0run] and timer overflow indicator sfr bit tcon2.1[t0full]. when sfr bit tcon2.0[t0run] is set, the counter starts counting on the next rising edge of the 2 khz rc lp oscillator and is stopped at the subsequent rising edge. this timer mode is used for e.g. interval timer calbration by the rom library functions (see [1] ?reference sfr registers? on page 144 ). timer 3 sets up a reloadable 8 bit timer holding the startup value in sfr tl1, timer reload value in sfr th1, timer run bit in sfr bit tcon2.4[t1run] and timer elapsed indicator in sfr bit tcon2.5[t1full]. note: this timer mode is not recommended for application usage. it is used by the rom library functions for calibration purpose. figure 32 timer mode 7 t2run t3run timer 3 timer 2 tl2 th2 tl3 th3 reload timer 3 reload rc-lp period baudrate strobe interrupt timer 2 & t2mask ie.6[eid] t2full ie.7[ea] ie.6[eid] ie.7[ea] t3full interrupt timer 3 & t3mask targetdatasheet.book page 104 monday, april 28, 2008 11:16 am
preliminary data sheet 105 v0.9, 2008-04-28 PMA7110 functional description 2.5.14 general purpose input/output (gpio) ten gpio pins are available and can either be used by the application for general purposes or are fixed assigned to one peripheral ( ?alternative port functionality? on page 109 ). when used as gpio pins they can be accessed directly by the processor. pullup and pulldown resistors are configurable on demand to allow wired-and and wired-or functions. all peripheral port pins are configured as input with the pullup resistor which will be enabled after a power on reset. pin-status will be kept during powerdown. 2.5.14.1 peripheral port basic configuration table 46 peripheral i/o port registers the following table shows the different possible configurations for the gpio- port. table 47 gpio port configuration note: in addition sfr bit ppsx defines the wakeup sensitivity for the external wakeup source (see ?external wakeup on pp1-pp4 and pp6-pp9? on page 109 ). the x in the table has to be replaced by any of 0 until 9(pp0 - pp9). sfr (abbr) addr access default value register p1dir 91 h rwuu/ ff h pp0-7 data direction register p1in 92 h r x/x pp0-7 data input register p1out 90 h rw u/ff h pp0-7 data out register p1sens 93 h rw u/00 h pp0-7 sensitivity register p3dir eb h rw u/03 h pp8-9 data direction register p3in ec h rx/x h pp8-9 data input register p3out b0 h rw u/03 h pp8-9 data out register p3sens ed h rw u/0 h pp8-9 sensitivity register ppdx ppox ppsx i/o pullup/ pulldown comment 00- outputnolow (sink) 0 1 - output no high (source) 1 0 - input no high-z (tri-state bidirectional) 1 1 0 input pullup weak-high (quasi bidirectional) 1 1 1 input pulldown weak-low (quasi bidirectional) targetdatasheet.book page 105 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 106 v0.9, 2008-04-28 table 48 sfr address 91 h : p1dir - io-port1 direction register table 49 sfr address eb h : p3dir - io-port3 direction register t table 50 sfr address 90 h : p1out - i/o-port1 data out register table 51 sfr address b0 h : p3out - i/o-port3 data out register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pd1_7 pd1_6 pd1_5 pd1_4 pd1_3 pd1_2 pd1_1 pd1_0 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 pd1_7 pd1_6 pd1_5 pd1_4 pd1_3 pp7 - pp3 i/o-port configuration/testmode(dmux6-dmux2 direction) 1: input port 0: output port pd1_2 pd1_1 pd1_0 pp2 - pp0 i/o-port configuration 1: input port 0: output port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. ppd9 ppd8 0/0 0/0 0/0 0/0 0/0 0/0 rw u/1 rw u/1 ppd9-8 pp-pp8 i/o-port configuration 1: input port 0: output port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1_7 p1_6 p1_5 p1_4 p1_3 p1_2 p1_1 p1_0 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 rw u/1 p1_7-p1_2 pp7 - pp2 data out/dmux6-dmux1 (data out/pullup enable) 1: input port 0: output port p1_1-p1_0 pp1 - pp0 data out / pullup enable bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. p3_1 p3_0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 rw u/1 rw u/1 p3_1 p3_0 pp9 data out / pullup enable pp8 data out / pullup enable targetdatasheet.book page 106 monday, april 28, 2008 11:16 am
preliminary data sheet 107 v0.9, 2008-04-28 PMA7110 functional description table 52 sfr address 93 h : p1sens - io-port1 sensitivity register the x in the table has to be replaced by either of 0 until 7. table 53 sfr address ed h : p3sens - io-port3 sensitivity register table 54 sfr address 92 h : p1in - io-port1 data in register table 55 sfr address ec h : p3in - io-port3 data in register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ps1_7 ps1_6 ps1_5 ps1_4 ps1_3 ps1_2 ps1_1 ps1_0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 ps1_x ppx i/o-port sensitivity 1b: pulldown is enabled if sfr p1dir.x==1 and p1out.x==1 0b: pullup is enable if sfr p1dir.x==1 and p1out.x==1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. ps3_1 ps3_0 r0/0 r0/0 r0/0 r0/0 r0/0 r0/0 rw u/0 rw u/0 ps3_1 pp9 i/o-port sensitivity 1b: pulldown 0b: pullup ps3_0 pp8 i/o-port sensitivity 1b: pulldown 0b: pullup bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pi1_7 pi1_6 pi1_5 pi1_4 pi1_3 pi1_2 pi1_1 pi_0 r x/x r x/x r x/x r x/x r x/x r x/x r x/x r x/x pi1_7-pi1_2 pp7-pp2 data in / testmode (dmux7-dmux2 in) pi1_1-pi1_0 pp1-pp0 data in bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. pi3_1 pi3_0 0/0 0/0 0/0 0/0 0/0 0/0 r x/x r x/x pi3_1 pp9 data in pi3_0 pp8 data in targetdatasheet.book page 107 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 108 v0.9, 2008-04-28 2.5.14.2 spike suppression on input pins to avoid metastabilities when reading the gpio pins, a synchronization stage is included and a two-stage spikefilter suppresses spikes, thus data is available to be read after a delay of maximum 2 systemclock periods. due to the synchronization stage the following possibilities might occur: ? signal duration (t signal ) < 1 systemclock period (1 t clk ): signal is surpressed ?1t clk < t signal < 2 t clk : undefined if supressed or passed ?t signal > 2 t clk : signal is available in p1in register targetdatasheet.book page 108 monday, april 28, 2008 11:16 am
preliminary data sheet 109 v0.9, 2008-04-28 PMA7110 functional description 2.5.14.3 external wakeup on pp1-pp4 and pp6-pp9 pp1-pp4 and pp6-pp9 can additionally be used as external wakeup sources if enabled by the wakeup-mask sfr bit exwum.x[mextwux] and configured as input pin by setting sfr bit p1dir.x[ppdx]. the internal pullup/pulldown resistor is enabled if sfr bit p1out.x[ppox] is set. sfr bit p1sens.x[ppsx] selects the sensitivity (high active/low active): table 56 external wakeup configuration the x in the table has to be replaced by either 1-4 or 5-9 (pp0-pp4, pp6-pp9). 2.5.14.4 alternative port functionality in the following table, the alternative port functionality is shown - which has higher priority than standard i/o port functionality. table 57 i/o port 1 - alternative functionality sfr settings description sfr bit p1dir.x[ppdx] = 1 sfr bit p1out.x[ppox]=1 sfr bit p1sens.x[ppsx] = 0 sfr bit exwum.x[mextwux] = 0 ppx configured as input, pullup enabled, wakeup occurs if ppx is forced to low externally. sfr bit p1dir.x[ppdx] = 1 sfr bit p1out.x[ppox] =1 sfr bit p1sens.x[ppsx] = 1 sfr bit exwum.x[mextwux] = 0 ppx configured as input, pulldown enabled, wakeup occurs if ppx is forced to high externally. pin function i/o description pp0 i2c-scl i i2c serial clock line configured to i2c clock pin if sfr bit cfg1.6 [i2cen] is set. weak-high has to be provided by an external pullup resistor or by the i2c master device. port pin i/o i/o standard i/o port functionality opmode1 i/o select operation mode pp1 i2c-sda i/o i2c serial data configured to i2c data pin if bit cfg1.6 [i2cen] is set. weak-high has to be provided either by the internal pullup resistor, by an external pullup resistor or by the i2c master device. port pin i/o i/o standard i/o port functionality wu0 i/o wake up by external wake up source opmode2 i/o select operation mode targetdatasheet.book page 109 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 110 v0.9, 2008-04-28 pp2 tx data out o if bit cfg1.4[rftxpen] is set to one, the manchester/biphase encoded data is delivered serial to pp2. an external device can process the data. port pin i/o i/o standard i/o port functionality wu1 i/o wake up by external wake up source pp3 spi_cs i/o spi bus interface chip select port pin i/o i/o standard i/o port functionality wu2 i/o wake up by external wake up source pp4 spi_miso i/o spi bus interface master in slave out port pin i/o i/o standard i/o port functionality wu3 i/o wake up by external wake up source pp5 spi_mosi i/o spi bus interface master out slave in port pin i/o i/o standard i/o port functionality pp6 spi_clk i/o spi bus interface clock port pin i/o i/o standard i/o port functionality wu4 i/o wake up by external wake up source pp7 port pin i/o i/o standard i/o port functionality wu5 i/o wake up by external wake up source pp8 port pin i/o i/o standard i/o port functionality wu6 i/o wake up by external wake up source pp9 ext_int i/o interrupt by external interrupt source port pin i/o i/o standard i/o port functionality wu7 i/o wake up by external wake up source pin function i/o description targetdatasheet.book page 110 monday, april 28, 2008 11:16 am
preliminary data sheet 111 v0.9, 2008-04-28 PMA7110 functional description 2.5.15 i 2 c- interface for communication between a external hardware and the PMA7110, a i 2 c master/slave interface is implemented. ? pp1 is used as a serial data line (sda) ? pp0 is used as a serial clock line (scl) ? PMA7110 responds to i 2 c- address 6c h or to a general call if enabled by addressing slave address 00 h . general call is enabled by setting sfr bit i2cc.6[gcen]. ? data transfer up to 100 kbit/s in standard mode, or 400 kbit/s in fast mode. to control i 2 c master/slave interface, the following registers are implemented: table 58 sfr i 2 c control, status und dataregister the basic i 2 c-bus configuration is set for both master- and slave mode. to allow bitlogic operations this register is readable and writeable. the contained bits are partially set by software and reset by hardware resp. set and reset by software itself. the control register is only applicable in master mode; in slave mode all functional steps are done automatically without external control. table 59 sfr address a2 h : i2cc - i 2 c control register sfr (abbr) addr access default value register i2cb b1 h rw 00/001 h i 2 c bitrate register. i2cc a2 hr rw 00/00 h i 2 c control register. i2cs 9b h r/rc 00/00 h i 2 c status register. i2cd 9a h rw 00/00 h i 2 c datain / dataout register. if written, data are stored in the i 2 c internal data transmit register - if read, data is read from the data receive register. flags tbf and rbf are available in status register. i2cm a3 hr rw 6c/6c h i 2 c mode register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. gcen inp ackdt acken pen rsen sen 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 gcen i 2 c general call enable. inp i 2 c interrupt/not-polling handling (0: interrupt, 1: polling mode). ackdt i 2 c acknowledge data (0: ack, 1: nack). acken i 2 c acknowledge sequence enable. pen i 2 c stop condition enable. targetdatasheet.book page 111 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 112 v0.9, 2008-04-28 table 60 sfr address 9b h : i2cs - i 2 c status register table 61 sfr address 9a h : i2cd - i2c data register table 62 sfr address b1 h : i2cb - i2c bitrate register rsen i 2 c repeated start condition enable. sen i 2 c start condition enable. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 am cd ov s rnw rack tbf rbf rc 0/0 rc 0/0 rc 0/0 rc 0/0 r 0/0 r 0/0 r 0/0 r 0/0 am address match - set if device address matches with received address byte cd i2c bus collision detected ov overflow bit - set if received byte has not been read out before next byte received; also set if byte has not been transmitted after writing new byte to register i2cd. in both cases, the old byte value is kept, the new byte is rejected. the bit is automatically cleared by hardware if i2cs is read. s i2c transmission in progress - set on occurrance of start condition and reset on occurrance of stop condition. rnw read/write bit information - states the actual state received with device address rack received acknowledge level - states the actual level of the received acknowledge (?0? if acknowledge, ?1? if not-acknowledge received). tbf transmit buffer full - set by hardware if register i2cd is written; cleared automatically if data byte is taken over by the shift register to be transmitted. rbf receive buffer full - set by hardware if a full data byte is received; cleared automatically if register i2cd is read. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i2cd.7 i2cd.6 i2cd.5 i2cd.4 i2cd.3 i2cd.2 i2cd.1 i2cd.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 i2cd.7-0 8 bit read/write data. access should be done after reading i2cs bits [tbd, rbf] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spib.7 spib.6 spib.5 spib.4 spib.3 spib.2 spib.1 spib.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 i2cb.7-0 8 bit bitrate data. targetdatasheet.book page 112 monday, april 28, 2008 11:16 am
preliminary data sheet 113 v0.9, 2008-04-28 PMA7110 functional description table 63 sfr address a3 h : i2cm - i2c mode register 2.5.15.1 slave mode sequence programming the slave i 2 c interface to enable the i 2 c interface, the sfr bit i2cc.6[gcen] has to be set. once the i 2 c interface has been enabled, the PMA7110 waits for a start condition to occur. after the PMA7110 received a start condition, the following received 7 bits are compared to the device address. when the address matches, the hardware automatically generates an acknowledge and sets sfr bit i2cs.7[am] and sfr bit i2cs.3[rnw]. depending on sfr bit i2cs.3[rnw], the following two different actions are executed: receive i 2 c-data ? if sfr bit i2cs.0[rbf] is set, one byte has been shifted to sfr i2cd. an acknowledge is automatically set by hardware as long as no receive buffer overflow (sfr bit i2cs.5[ov]) has occurred. ? if sfr bit i2cs.4[s] is set, a stop condition has occurred; the transmission is closed by the master device. ? if sfr bit i2cs.7[am] is set, a restart condition has been set and a matching address has been received; in case of a write access, a branch to the transmit data subroutine has to be performed. transmit i 2 c data ? data to be transmitted has to be written to sfr i2cd. sfr bit i2cs.1[tbf] is reset if data is taken over by the shift-register and new data may be written to sfr i2cd. if no data is provided, the i 2 c interface automatically sets line scl to low until data is written to sfr i2cd (slave device gains access over line scl). ? if sfr bit i2cs.4[s] is set, the transmission process has been terminated by the master and the transmission subroutine can be left. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a7 a6 a5 a4 a3 a2 a1 n.u. rw 0/0 rw 1/1 rw 1/1 rw 0/0 rw 1/1 rw 1/1 rw 0/0 r 0/0 i2cm.0-7 8 bit address data. targetdatasheet.book page 113 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 114 v0.9, 2008-04-28 2.5.15.2 general call sequence if a general call address is sent and bit i2cc.6 [gcen] in control register is set the i2c- bus behaves like a slave receiver, i.e. the same procedure may be taken. the defined general call protocol has to be done by software. 2.5.15.3 master mode sequence after enabling the i 2 c bus module and configuration as master device, it waits for fur- ther actions given by the control register (i2cc and simultaneously for a start condition from other master devices; in the later case the master behaves like a slave, i.e. the same procedure described above may be taken. control over the i2c-bus is only taken if the i2c-bus is in idle state and bit i2cc.0 [sen] (start enable in the control register plus the address of the wanted device including the access direction bit rnw in status register (i2cs.3 is set by software. the start condition and the following address byte is transmitted immediately on scl and sda. an existing slave with the according device address responds with an acknowledge, whereby bits ie.4 [ei2c] and i2cs.2 [rack] in status register will be set accordingly. after that the master may transmit (write data to data register) or receive (read data register after reception) data. after data reception the master has to set an acknowledge. this is done by setting bit i2cc.3 [acken] and i2cc.4 [ackdt] in control register. please see table 30 "sfr address a8 h : ie-interrupt enable register" on page 76 and table 31 "sfr address b8 h : ip-interrupt priority register" on page 77 . 2.5.16 serial peripheral interface spi the PMA7110 supports a 2, 3 or 4 wires bus protocol. ? high speed synchronous data transfer (up to 1.125 mbit @ 18 mhz clock) ? four programmable bit rates through prescaler ? 2-wire bus for half duplex transmission; a serial clock line (spi_clk) and concatenated data line (spi_miso,spi_mosi) ? 3-wire bus for full duplex transmission; a serial clock line (spi_clk) and two serial data lines (spi_miso,spi_mosi) ? a 4-wire bus for full duplex transmission plus handshaking can be implemented by utilizing also the chip select (spi_cs). this pin can be used for indicating the beginning of a new byte sequence ? master or slave operation targetdatasheet.book page 114 monday, april 28, 2008 11:16 am
preliminary data sheet 115 v0.9, 2008-04-28 PMA7110 functional description ? clock control - polarity (idle low/high) and phase (sample data with rising/falling clock edge) are programmable ? bit width (1 to 8 bits) and bit order (msb or lsb first) are configurable ? compatible to ssc (high speed synchronous serial interface) and standard spi interfaces ? protocol is defined by software the serial peripherial interface, also known as spi, is a very simple synchronous interface to transfer data on a serial bus, connecting an intelligent master controller with general-purpose slave circuits like slave controller, rams, memories and so on. a simple 2-wire (half duplex mode) or 3-wire (full duplex mode) bus is used for communication. the spi will operate in the master mode normally, thus the spi has to drive the clock line (spi_clk). therefore the spi encloses a dedicated bit rate generator. table 64 sfr address f4 h : spic - spi control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. csmon dord mstr cpol cpha n.u. n.u. 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 0/0 0/0 dord ?data order? dord = 0 ... lsb is transmitted and received first dord = 1 ... msb is transmitted and received first mstr ?master/slave select? mstr = 0 ... spi is configured as slave device (controls port miso) mstr = 1 ... spi is configured as master device (controls port sck, mosi) cpol ?clock polarity? - defines the initial state of spi clock line sck cpol = 0 ... idle clock line is low and leading clock edge is a low to high transition cpol = 1 ... idle clock line is high and leading clock edge is a high to low transition cpha ?clock phase? determines whether data is active with rising or falling edge of spi clock sck. cpha = 0 ... transmission starts without a rising or falling edge on spi clock; with first edge detected, the first data bit is latched, with the following edge data are shifted. cpha = 1 ... a rising or falling edge is generated on spi clock before data are set; with the following clock edge data are latched before shifted on with consecutive one. targetdatasheet.book page 115 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 116 v0.9, 2008-04-28 table 65 sfr address f5 h :spid - sfr spi data register table 66 sfr address f6 h : spim - spi mode register table 67 sfr address f7 h : spis - spi status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spid.7 spid.6 spid.5 spid.4 spid.3 spid.2 spid.1 spid.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fl n.u. n.u. algn n.u. dws2 dws1 dws0 rw 0/0 0/0 0/0 rw 0/0 0/0 rw 0/0 rw 0/0 rw 0/0 fl spi force level fl=0 ... spi_miso, spi_mosi and spi_clk pullup driven weak high level fl=1 ... spi_miso, spi_mosi and spi_clk active driven high level dws2-0 ?data width selection (bit 2-0)? defines the amount of transmitted bits per data byte. if set to ?000?, a whole data byte (8 bits) is transmitted (spi standard). if only a byte fragment should be transferred, it depends on spic.5 [dord] whether the upper dws.2-0 bits of data register spid are transmitted or the lower one algn data allign (0: right, 1: left) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sre ste spe sscc scsd scss srbf stbe rc 0/0 r 1/1 rc 0/0 rc 0/0 rc 0/0 rc 0/0 rc 0/0 r 1/1 sre ?spi receive error? is set by hardware if a new data frame is completely received but the previous data was not read out from the receive data buffer spid (data will be overwritten). ste ?spi transmit completed? (no further data to transmit) spe ?spi phase error? is set by hardware if the incoming data at pin miso (master mode) respectively mosi (slave mode) sampled with cpu clock, changes between 1 sample before and 2 samples after latching edge of the clock signal. sscc ?spi slave communication corrupt? scss ?spi chip select latch status? if register spic is read, this bit is set with the actual state of pp5/spi-mosi. css is set, if an rising edge is detected on pp5/spi-mosi pin (spi transmission completed). scsd ?spi chip select detected? targetdatasheet.book page 116 monday, april 28, 2008 11:16 am
preliminary data sheet 117 v0.9, 2008-04-28 PMA7110 functional description table 68 sfr address f3 h : spib - spi bitrate register (11 bit cascaded register) 2.5.17 programming mode operation in programming mode the PMA7110 is accessible as a slave using the i2c interface. the device is operating using the 12 mhz rc hf oscillator as clock source. to avoid programming failures all programming mode commands are protected by a 16 bit crc at the end of each command ( ?16bit crc (cyclic redundancy check) generator/checker? on page 86 shows details about the used crc polynom). the checksum has to be calculated over all bytes in the command excluding the PMA7110 i2c device address. programming mode commands: ? flash write line ? flash erase ? flash check erase status ? flash read line ? flash set lockbyte 3 ? read status 2.5.17.1 flash write line the flash write line command writes 32 bytes to the flash, start address is a multiple of 20 h . ? if transferring the start address, the lower 5 bits are cleared automatically. ? if less than 32 data bytes are received, the contents of the previous write access are written into the flash. srbf ?spi receive buffer full? is set by hardware if a data byte is received completely; the receive buffer is ready to beread. stbe ?spi transmit buffer empty? is reset by hardware if register spid is written and automatically set if data byte is transferred to spi internal shift register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spib.7 spib.6 spib.5 spib.4 spib.3 spib.2 spib.1 spib.0 w 0/0 w 0/0 w 0/0 w 0/0 w 0/0 w 0/0 w 0/0 w 0/0 spib.7 - spib.0 bit 7 - bit 0 targetdatasheet.book page 117 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 118 v0.9, 2008-04-28 ? if an already written section in the flash gets re-written (without being erased before), the resulting data is undefined. note: after the stop condition (p) is received the data is programmed into the flash. during the programming time incoming i2c commands are not acknowledged. figure 33 flash write line command adrhi : msb of the flash address to write to. adrlo : lsb of the flash address to write to (has to be a multiple of 20 h ). data0 ... data31: this data is written into the flash memory starting at the specified address. data0 is written at the lowest specified address. crch : msb of the crc sum. crcl : lsb of the crc sum. 2.5.17.2 flash erase the flash erase command erases 1 to 5 sectors of the flash. note: after the stop condition (p) is received the selected flash sectors are being erased. during the erase time incoming i2c commands are not acknowledged. figure 34 flash erase command table 69 parameter: sect bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. sector4 sector3 sector2 sector1 sector0 sector4 protected area, don?t care sector3 protected area, don?t care sector2 protected area, don?t care 0x6c s a a adrhi p a crch a adrlo a .... a data0 a data31 a crcl 0x6c s a a crch p a a crcl 0xa2 a sect targetdatasheet.book page 118 monday, april 28, 2008 11:16 am
preliminary data sheet 119 v0.9, 2008-04-28 PMA7110 functional description crch : msb of the crc sum crcl : lsb of the crc sum sector1 1: erase user data sector 0: don?t erase user data sector sector0 1: erase code sector 0: don?t erase code sector targetdatasheet.book page 119 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 120 v0.9, 2008-04-28 2.5.17.3 flash check erase status this function returns the status of the selected flash sector(s). the time required for the checking of the sectors depends on the selected sectors. note: after the first stop condition (p) is received the selected flash sectors are checked. during this time incoming i2c commands are not acknowledged. figure 35 flash check erase status command table 70 parameter: sect crch : msb of the crc sum. crcl : lsb of the crc sum. table 71 return value: status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. sector4 sector3 sector2 sector1 sector0 sector4 protected area, thus don?t care sector3 protected area, thus don?t care sector2 protected area, thus don?t care sector1 1: check if user data sector is erased 0: don?t check user data sector sector0 1: check if code sector is erased 0: don?t check code sector bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. sector4 sector3 sector2 sector1 sector0 sector4 1: at least one bit is set in the sector 0: sector is erased or untested sector3 1: at least one bit is set in the sector 0: sector is erased or untested sector2 1: at least one bit is set in the sector 0: sector is erased or untested sector1 1: at least one bit is set in the sector 0: sector is erased or untested sector0 1: at least one bit is set in the sector 0: sector is erased or untested 0x6d s a status p na pause > 35ms 0x6c s a a crch p a a crcl 0xa3 a sect a crch crcl a targetdatasheet.book page 120 monday, april 28, 2008 11:16 am
preliminary data sheet 121 v0.9, 2008-04-28 PMA7110 functional description 2.5.17.4 flash read line the contents of the flash memory can be read out via the i2c interface. if lockbyte 2 is set, reading of code sector will only yield 0 h , but the lockbyte 2 itself can still be read for validating the result. figure 36 flash read line command adrhi : msb of the address to start the read access. adrlo : lsb of the read address. data0 : value that has been read from the specifed address data31 : value that has been read from the specified address + 31. crch : msb of the crc sum. crcl : lsb of the crc sum. 2.5.17.5 flash set lockbyte 2 lockbyte 2 protect the code sector. after the lockbyte 2 is set by the keil programmer, a startup in debug mode or programming mode is not possible any more. 2.5.17.6 flash set lockbyte 3 this command sets the lockbyte 3 protecting the flash user configuration sector (sector 1). after the lockbyte 3 is set, a startup in debug mode or programming mode is not possible any more (see ?? on page 121 for details). note: it is required to set lockbyte 2 (code sector) to enable lockbyte 3 to become effective. figure 37 flash set lockbyte 3 command 0x6c s a a a 0x6d s a a data0 data31 .... adrhi adrlo sr p a crch a crcl 0x6c s a a 0x44 p a a 0x3b 0xa1 targetdatasheet.book page 121 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 122 v0.9, 2008-04-28 2.5.17.7 read status this function is intended to read out the status of the previous executed functions (pass/fail). it can be called whenever desired to verify if there were errors since the last read status call. . figure 38 read status command table 72 return value: status crch : msb of the crc sum crcl : lsb of the crc sum. figure 39 i 2 c-commands legend bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmdcnt3 cmdcnt2 cmdcnt1 cmdcnt0 errcnt1 errcnt0 invcmdl crcfail cmdcnt3-0 counter indicates the number of executed commands since the first detected error. 1111b: 15 commands or more 1110b: 14 commands ... 0001b: 1 command 0000b: error occured in last command errcnt1-0 counter of erroneous events since the last read status call 11b: three or more errors 10b: two errors 01b: one error 00b: no error invcmdl 1: invalid command length or execution fail since the last read status call 0: no invalid command length or execution fail occured since the last read status call crcfail 1: crc failure detected since the last read status call 0: no crc error occured since the last read status call 0x6d s a status p na pause > 9s 0x6c s a a 0x14 p a a 0x9e 0xa4 a crch crcl a from master to slave s start condition na not acknowledg e from slave to master p stop condition a acknowledge sr repeated start condition, may be replaced by stop-start condition targetdatasheet.book page 122 monday, april 28, 2008 11:16 am
preliminary data sheet 123 v0.9, 2008-04-28 PMA7110 functional description 2.5.18 debug mode operation 2.5.18.1 debug special function registers table 73 debug mode sfrs: 2.5.18.2 debugging facility during program execution, the program counter (pc) of the microcontroller is continuously compared with the contents of the dbchx + dbclx registers. the dbchx + dbclx registers can be set to addresses in the flash or the rom code area. in case of a match, the pc is automatically set to the address given in dbthx + dbtlx, and program execution is continued. the x in the upper content is 0 or 1. rom debug function the debug function mainly consists of a debug handler and a single stepper. the debug handler processes the i 2 c communication and debug command interpretation. the debug commands setsfr , readsfr , setdata, readdata and setpc, readpc are executed directly by the debug handler. the debug commands single step , run interruptible and run until breakpoint are executed by the single stepper. the single stepper fetches the current opcode and enables opcode execution depending on the debug command. to enable single stepping of branch instructions, two sets of debug registers are implemented. afterwards, the debug handler is entered again. sfr (abbr) addr access default value register dbcl0 94 h rw 00 h /00 h debug compare register 0 (low) dbch0 95 h rw 00 h /00 h debug compare register 0 (high) dbtl0 96 h rw 00 h /00 h debug target register 0 (low) dbth0 97 h rw 00 h /00 h debug target register 0 (high) dbcl1 9c h rw 00 h /00 h debug compare register 1(low) dbch1 9d h rw 00 h /00 h debug compare register 1 (high) dbtl1 9e h rw 00 h /00 h debug target register 1 (low) dbth1 9f h rw 00 h /00 h debug target register 1 (high) targetdatasheet.book page 123 monday, april 28, 2008 11:16 am
PMA7110 functional description preliminary data sheet 124 v0.9, 2008-04-28 2.5.18.3 debugger commands setsfr : set an sfr to a user-defined value. exception: it is not possible to set the sfrs used by the debug function itself (gpr3, gpr4, gpr5, dbcxx). adr : represents the address of the sfr to be set. data : this value has to be put into the sfr address specified by adr . readsfr: read the value of one sfr. adr : represents the address of the sfr to be read. data : this value was read on the sfr address specified by adr . setdata : set one byte in ram to a user-defined value. adr : represents the address of the internal data memory to be set. data : this value that has to be written into the internal data memory byte specified by adr . readdata : read one byte of the ram. adr : represents the address of the internal data memory location to be read. data : this value was read from the internal data memory address specified by adr . setpc: set the program counter to a user-defined value. adrhi: msb of the new program counter. adrlo: lsb of the new program counter. 0x6c s a a adr p a 0x00 data a 0x6c s aadr p a 0x03 a 0x6d s a data p pause > 9s na 0x6c s a a adr p a 0x06 data a 0x6c s aadr p a 0x09 a 0x6d s a data p pause > 9s na 0x6c s a a adrhi p a 0x0c adrlo a targetdatasheet.book page 124 monday, april 28, 2008 11:16 am
preliminary data sheet 125 v0.9, 2008-04-28 PMA7110 functional description readpc: reads the program counter pchi: msb of the program counter. pclo: lsb of the program counter. singlestep: execute one opcode instruction and return to the debug handler run interruptible: the function consists of device internal consecutive single steps until any i2c command is received on the bus. compared to running the program in realtime this function has a slower execution speed by a factor of about 1/50, dependent on the executed program. run until breakpoint: the debugged program is executed without single steps in realtime. this enables debugging of runtime critical functions like rf transmission or lf data receiving. the execution is stopped when the pc matches one of the two hardware breakpoints. if none of these breakpoints is hit the communication to the debugger is lost. bp0 h : msbyte of the breakpoint register 0. bp0 l : lsbyte of the breakpoint register 0. figure 40 i 2 c-commands legend 0x6c s a p a 0x0f 0x6d s a pchi p pause > 9s na apclo 0x6c s a a 0x12 p 0x6c s a a 0x15 p 0x6c s a a bp0 h p a 0x18 bp0 l a from master to slave s start condition na not acknowledg e from slave to master p stop condition a acknowledge sr repeated start condition, may be replaced by stop-start condition targetdatasheet.book page 125 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 126 v0.9, 2008-04-28 3 reference 3.1 electrical data 3.1.1 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 74 absolute maximum ratings # parameter symbol limit values unit remarks min. max. a1 supply voltage v batmax -0.3 +4.0 v a2 operating temperature t j -40 +125 c max 24 hrs accumulated over life time a3 storage temperature t s -40 +100 c max 1000 hours a5 esd hbm integrity v hbm 2kv all pins according to esd standard jedec eia / jesd22-a114- b a6 esd cdm integrity v cbm 500 v all pins (according to esda stm 5.3.1) 750 v corner pins (according to esda stm 5.3.1) a7 latch up i lu -100 +100 ma aec-q100 (transient current) a8 input voltage at digital input pins v inmax -0.3 v bat +0.3 v a9 input and output current for digital i/o pins i iomax 4ma a10 lf receiver input current i lfin 4ma a11 xtal input volage v inxt -0.3 v reg +0.3 v targetdatasheet.book page 126 monday, april 28, 2008 11:16 am
preliminary data sheet 127 v0.9, 2008-04-28 PMA7110 reference 3.1.2 operating range within the operational range the ic operates as explained in the circuit description. table 75 operating range # parameter symbol limit values unit remarks min. typ. max. b1 supply voltage v bat1 2.1 3.6 v measurement of, temperature and external sensor. operation of lf receiver v bat2 1.9 3.6 v battery measurements, microcontroller, rf transmitter v batfl 2.5 3.6 v flash programming b4 ambient temperature t amb -40 85 c normal operation t flc 0 0~35 c flash code sector programming t fld 0 0~35 c flash data sector programming targetdatasheet.book page 127 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 128 v0.9, 2008-04-28 3.1.3 product characteristics product characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. typical characteristics are the median of the production. supply voltage: v bat = 1.9v ... 3.6v, unless otherwise specified ambient temperature: t amb = -40c ... +85c, unless otherwise specified table 76 temperature sensor characteristics table 77 battery sensor characteristics table 78 supply currents # parameter symbol limit values unit test conditions remarks min. typ. max. q1 measurement error t error -3 +3 c t=-20 ... 70c v bat = 2.1 ... 3.6v q2 measurement error -5 +5 c t=-40 ... 85c v bat = 2.1 ... 3.6v # parameter symbol limit values unit test conditions remarks min. typ. max. p1 measurement error v error -100 100 mv # parameter symbol limit values unit test conditions remarks min. typ. max. c1a supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 8,9 11 12 9 12 15 ma ma ma @pout=5/8/10dbm, v bat =3v, t=-40c sfr divic = 0x03, f=315mhz c1b supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 9,2 11,5 12,9 9,5 12 15 ma ma ma @pout=5/8/10dbm, v bat =3v, t=-40c sfr divic = 0x03, f=434mhz c2a supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 9,7 12,2 12,8 10 14 18 ma ma ma @pout=5/8/10dbm, v bat =3v, t=25c sfr divic = 0x03, f=315mhz targetdatasheet.book page 128 monday, april 28, 2008 11:16 am
preliminary data sheet 129 v0.9, 2008-04-28 PMA7110 reference c2b supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 9,9 12,3 13,8 10 14 18 ma ma ma @pout=5/8/10dbm, v bat =3v, t=25c sfr divic = 0x03, f=434mhz c3a supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm tbd tbd tbd tbd tbd tbd ma ma ma @pout=5/8/10dbm, v bat =3v, t=85c sfr divic = 0x03, f=315mhz c3b supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm tbd tbd tbd tbd tbd tbd ma ma ma @pout=5/8/10dbm, v bat =3v, t=85c sfr divic = 0x03, f=434mhz c4a supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 11,3 12,8 16,8 tbd tbd tbd ma ma ma @pout=5/8/10dbm, v bat =3v, t=-40c sfr divic = 0x03, f=868mhz c4b supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 11,3 13,4 16,7 tbd tbd tbd ma ma ma @pout=5/8/10dbm, v bat =3v, t=-40c sfr divic = 0x03, f=915mhz c4c supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 11,8 12,9 16,9 14 18 24 ma ma ma @pout=5/8/10dbm, v bat =3v, t=25c sfr divic = 0x03, f=868mhz c4d supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm 12,6 15,3 17,1 14 18 24 ma ma ma @pout=5/8/10dbm, v bat =3v, t=25c sfr divic = 0x03, f=915mhz c4e supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm tbd tbd tbd tbd tbd tbd ma ma ma @pout=5/8/10dbm, v bat =3v, t=85c sfr divic = 0x03, f=868mhz c4f supply current rf transmission fsk modulation i fsk5dbm i fsk8dbm i fsk10dbm tbd tbd tbd tbd tbd tbd ma ma ma @pout=5/8/10dbm, v bat =3v, t=85c sfr divic = 0x03, f=915mhz note: matching circuit as used in the 50 ohm-output evaluation board at the specified frequency. tolerances of the passive elements not taken into account c5 supply current power down i pd 500 700 na v bat = 3.0v, t= 25c 2.6 9 a v bat = 3.0v, t= 85c # parameter symbol limit values unit test conditions remarks min. typ. max. targetdatasheet.book page 129 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 130 v0.9, 2008-04-28 c7 supply current thermal shutdown i tshd n.u. n.u. n.u. a c8 supply current idle (sfr divic = 0x00, systemclock = 12 mhz rc osc.) i idle tbd ma v bat = 3.0v, t= 25c tbd ma v bat = 3.0v, t= 85c c9 supply current run (sfr divic = 0x00, systemclock = 12 mhz rc osc.) i run tbd ma v bat = 3.0v, t= 25c tbd ma v bat = 3.0v, t= 85c # parameter symbol limit values unit test conditions remarks min. typ. max. targetdatasheet.book page 130 monday, april 28, 2008 11:16 am
preliminary data sheet 131 v0.9, 2008-04-28 PMA7110 reference table 79 rf transmitter characteristics the rf transmitter is characterized on the testboard with 50 ohm matching network for specified frequency. tolerances of the passive elements not taken into accoun. under this condition, the application is compliant to standards etsi en 300 220 and fcc 15.231a/b/e. # parameter symbo l limit values unit test conditions remarks min. typ. max. d1 transmit frequency f tx 300 433 865 902 320 450 870 928 mhz mhz mhz mhz d2 output power transformed to 50 ohm p 5dbm p 8dbm p 10dbm 4 7 9 5 8 10 6 9 11 dbm dbm dbm v bat =3v, t=25c d3 low temp. output power change dp lt 1dbv bat =3v, t=-40c, nominal output power p 5dbm d4 high temp. output power change dp ht -1.5 db v bat =3v, t=85c, nominal output power p 5dbm d5 supply voltage dependent output power change dp v1v9 -5.5 db v bat =1.9v, t=25c, nominal output power p 5dbm d6 supply voltage dependent output power change dp v2v5 -1.8 db v bat =2.5v, t=25c, nominal output power p 5dbm d7 supply voltage dependent output power change dp v3v6 1.8 db v bat =3.6v, t=25c nominal output power p 5dbm d8 data rate 32 kbps 64kchips/s d9 carrier to spurious ratio (incl. harmonics) @d1=315/915mhz -28 dbc fcc 15.231a/e rbw=100khz 2nd -10th harmonic d10 carrier to noise ratio @d1=315/915mhz -20 dbc fcc 15.231a/e rbw=100khz measured at frequency edge: 0,25%*f c for 315mhz 0,5%*f c for 915mhz f c : carrier frequency targetdatasheet.book page 131 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 132 v0.9, 2008-04-28 d11 ssb phase noise @d1=315mhz -95 -93 -97 -120 -136 tbd tbd tbd tbd tbd dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz rbw = 100khz, +25c @ 10khz offset, @ 100khz offset, @ 250khz offset, @ 1mhz offset, @ 10mhz offset, d12 ssb phase noise @d1=434mhz -93 -90 -91 -113 -132 tbd tbd tbd tbd tbd dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz rbw = 100khz, +25c @ 10khz offset, @ 100khz offset, @ 250khz offset, @ 1mhz offset, @ 10mhz offset, d13 ssb phase noise @d1=868mhz -87 -85 -88 -110 -134 tbd tbd tbd tbd tbd dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz rbw = 100khz, +25c @ 10khz offset, @ 100khz offset, @ 250khz offset, @ 1mhz offset, @ 10mhz offset, d14 ssb phase noise @d1=915mhz -86 -85 -87 -109 -135 tbd tbd tbd tbd tbd dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz rbw = 100khz, +25c @ 10khz offset, @ 100khz offset, @ 250khz offset, @ 1mhz offset, @ 10mhz offset, d15 spurious and out band emission @d1=434/868mhz -54 dbm en300220 (eur) rbw = 10khz 47-74mhz, 87.5-118mhz, 174-230mhz, 470-862mhz d16 spurious and out band emission @d1=434/868mhz -36 dbm en300220 (eur) rbw = 10khz other < 1ghz d17 spurious and out band emission @d1=434/868mhz -30 dbm en300220 (eur) rbw=10khz other >1ghz note: matching circuit as used in the 50 ohm-output testboard at the specified frequency. tolerances of the passive elements not taken into account targetdatasheet.book page 132 monday, april 28, 2008 11:16 am
preliminary data sheet 133 v0.9, 2008-04-28 PMA7110 reference table 80 lf receiver, v bat =2.1-3.6v # parameter symbol limit values unit test conditions, remarks min. typ. max. e1 lf baseband sensitivity gain setting 1 s lf1 1.2 mv pp input signal level required to achieve a ber better than 0.1% (100% square am modulation, datarate 4000 bit/s) sfr lfrx0: tbd sfr lfcdm: tbd sfr lfcdflt: tbd e2 lf baseband sensitivity gain setting 2 s lf2 120 mv pp input signal level required to achieve a ber better than 0.1% (100% square am modulation, datarate 4000 bit/s) sfr lfrx0: tbd sfr lfcdm: tbd sfr lfcdflt: tbd e3 datarate dr lf 2000 4000 bit/s e4 datarate error dr error 2% e5 carrier frequency f clf 120 125 130 khz e6 lf current consumption i lf_afe 2av bat = 3.0v, t= 25c, lf input signal smaller than carrier detection level (12 mhz rc hf osc. and lf baseband off) i lf_bb tbd a v bat = 3.0v, t= 25c, lf input signal higher than carrier detection level or enabled by sfr bit lfcdflt.[cdfm1-0] = 11b (12 mhz rc hf osc. and lf baseband on) e7 input dynamic range dr lf 70 db sensitivity gain setting 1 (#e1), agc enabled e9 agc attack time t agcatt 200 900 s @continous wave signal targetdatasheet.book page 133 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 134 v0.9, 2008-04-28 e10 agc decay slew rate t agcdec 35 v/s sfr bit lfrx0.7-6[agctcd1- 0] = 00b 70 v/s sfr bit lfrx0.7-6[agctcd1- 0] = 01b 140 v/s sfr bit lfrx0.7-6[agctcd1- 0] = 10b e11 settling time t set 4 ms power on settling time of internal nodes. 6 x 2 khz rc oscillator cycles. min/max tolerances from table 83 apply. e12 input capacitance c inlf t.b.d 10 t.b.d pf e13 differential input resistance r inlf t.b.d 420 t.b.d kohm agc disabled e14 preamble length t preamble 3 ms manchester coded input signal. datarate 4kbit/s f1 lf carrier detector threshold gain setting 1. dl cd1 0.2 tbd 2.5 mv pp minimum carrier pulse length 1ms sfr lfrx0: tbd sfr lfcdm: tbd sfr lfcdflt: tbd 1.2 3 7.5 mv pp minimum carrier pulse length 1ms sfr lfrx0: tbd sfr lfcdm: tbd sfr lfcdflt: tbd f2 lf carrier detector threshold gain setting 2 dl cd2 20 50 120 mv pp minimum carrier pulse length 1ms sfr lfrx0: tbd sfr lfcdm: tbd sfr lfcdflt: tbd 80 200 480 mv pp minimum carrier pulse length 1ms sfr lfrx0: tbd sfr lfcdm: tbd sfr lfcdflt: tbd f3 carrier detector freeze hold time t cdcfh 50 ms worst case @ 85c if calibration freeze bit sfr bit lfcdm.3[lfenfc tc] is set # parameter symbol limit values unit test conditions, remarks min. typ. max. targetdatasheet.book page 134 monday, april 28, 2008 11:16 am
preliminary data sheet 135 v0.9, 2008-04-28 PMA7110 reference f4 carrier detector filter time t cdflt tbd tbd s sfr bit lfcdflt.4-5[cdft1- 0] = 00b tbd tbd s sfr bit lfcdflt.4-5[cdft1- 0] = 01b tbd tbd s sfr bit lfcdflt.4-5[cdft1- 0] = 10b tbd tbd s sfr bit lfcdflt.4-5[cdft1- 0] = 11b # parameter symbol limit values unit test conditions, remarks min. typ. max. targetdatasheet.book page 135 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 136 v0.9, 2008-04-28 table 81 crystal oscillator table 82 12 mhz rc hf oscillator table 83 2khz rc lp oscillator # parameter symbol limit values unit test conditions remarks min. typ. max. g1 crystal startup time t xtal 1.2 ms ifx testboard with crystal nx5032sd exs00a- 02825 c l =12pf , f crystal = 18,08mhz g2 crystal oscillator startup delay time t xtaladj 0 1750 s progammable in 250s steps sfr xtcfg g3 crystal frequency f xtal 18 20 mhz g4 paracitic capacitance c pcbmax 4 pf determined by pcb layout g5 serial resistance of the crystal r rmax --60ohmf crystal =19~20mhz r rmax --80ohmf crystal =18~19mhz g6 input inductance xtalout l osc 2.2 uh g7 crystal fine tuning capacitance c tune 40 pf selectable with 156 ff resolution (8 bits) # parameter symbol limit values unit test conditions remarks min. typ. max. h1 operating frequency f rchf 11.64 12.00 12.36 mhz v bat = 3.0v, t= 25c h3 overall drift df rchf +/- 5 % # parameter symbol limit values unit test conditions remarks min. typ. max. j1 operating frequency f rclp 1.3 2 2.8 khz v bat = 3.0v, t= 25c j2 overall drift df rclp +/- 7 % targetdatasheet.book page 136 monday, april 28, 2008 11:16 am
preliminary data sheet 137 v0.9, 2008-04-28 PMA7110 reference table 84 interval timer # parameter symbol limit values unit test conditions remarks min. typ. max. k1 wake up interval timer range t wu 0.035 332.8 s adjustble with resolution of 8 bit. k2 wake up interval timer step t wust 0.05 1 s k3 frequency calibration error f itce +/- 5 % t wust =0.5s, systemclock = xtal targetdatasheet.book page 137 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 138 v0.9, 2008-04-28 table 85 power on reset # parameter symbol limit values unit test conditions remarks min. typ. max. l1 power on reset level v por 0.2 0.4 1.7 v minimum supply voltage level measured at pin v reg for a valid logic low at power on reset circuit l2 power on release level v thr 1.7 1.8 v measured at pin v reg l3 power on reset time t por 0.25 10 ms l4 brown out detect level in run state v brd 1.7 1.8 v measured at pin v reg l5 brown out detect level in power down and thermal shutdow n v pdbr 0.7 1.7 v measured at pin v reg l6 mode selection time t mode 2.5 ms l7 minimum detectable brown out glitch in run state t brd 1s l8 minimum detectable brown out glitch in power down and thermal shutdow n t brdpd s not used targetdatasheet.book page 138 monday, april 28, 2008 11:16 am
preliminary data sheet 139 v0.9, 2008-04-28 PMA7110 reference table 86 voltage regulator table 87 vmin detector # parameter symbol limit values unit test conditions remarks min. typ. max. m1 regulated output voltage in run state v reg 2.3 2.5 2.75 v v bat = 2.5v-3.6v, i reg =0.1-10ma 1) 1) the voltage regulator is designed to supply only the internal blocks of the PMA7110 and not designed to drive any external circuitry, thus only the decoupling cap may be connected to the pin v reg . a 100nf decoupling cap is recommended for proper operation. m2 regulated output voltage at low battery in run state v reglow 1.8 2.5 v v bat = 1.9v-2.5v, i reg =0.1-8.5ma 1) m4 regulated output voltage in power down thermal shut down v reglp 1.7 2.75 v i regpd = max. 40ua 1) # parameter symbol limit values unit test conditions, remarks min. typ. max. n1 low battery threshold warning level th lbat 2.0 2.1 2.2 v used by rom library functions only targetdatasheet.book page 139 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 140 v0.9, 2008-04-28 table 88 6k flash code memory data table 89 2 times 128 byte flash user data memory # parameter symbol limit values 1) 1) this is only valid for storage temperature from -40c to +125c for max. 1000 hours. unit test conditions remarks min. typ. max. o1 temperature range erase/program tr fl 00 ~ 35 c o2 erase/program supply voltage range regulated @pad vddd @pad vbat v flvddd v flbat 2.3 2.5 2.5 v v o3 endurance data retention @25c en flcode t rcode 400k 40 1m cycles yrs programming /erase cycles per sector or wordline o4 erase time 102 ms rc-hf-oscillator @12mhz o5 write time/line 2.2 ms rc-hf-oscillator @12mhz line=32byte # parameter symbol limit values 1) unit test conditions remarks min. typ. max. o6 temperature range erase/program tr fl 0~35 c o7 erase/program supply voltage range regulated @pad vddd @pad vbat v flvddd v flbat 2.3 2.5 2.5 v v o8 endurance data retention en flcode @25c t rcode @85c 100 40 500 kcycles yrs programming /erase cycles per sector or wordline retention is a function of endurance targetdatasheet.book page 140 monday, april 28, 2008 11:16 am
preliminary data sheet 141 v0.9, 2008-04-28 PMA7110 reference o9 erase time 102 ms rc-hf-oscillator @12mhz o10 write time/line 2.2 ms rc-hf-oscillator @12mhz line=32byte 1) this is only valid for storage temperature from -40c to +125c for max. 1000 hours. targetdatasheet.book page 141 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 142 v0.9, 2008-04-28 table 90 adc interface table 91 tmax detector table 92 digital i/o pin # parameter symbol limit values unit test conditions remarks min. typ. max. p1 adc input voltage range vr adc gnd vadc p2 adc resolution r adc 10 bit p3 offset correction range r offc 6bit p4 adc clock frequency f adc 0.5 1 20 mhz p5 differential non- linearity dnl -0.5 0.5 lsb p6 integral non- linearity inl -1 1 lsb p7 noise n adc 15 v rms p8 non-ratiometric offset voltage with supply voltage 1 ov nr -1.5 1.5 lsb measured at any constant temperature between -20 and 70c 1.) extrapolate offset voltage vs. supply voltage to find the intersection with the y-axis (supply voltage =0). this is the non-ratiometric part of the offset voltage. # parameter symbol limit values unit test conditions remarks min. typ. max. t1 thermal shutd ownrelease temperature t rel tbd tbd tbd c used by rom library functions only # parameter symbol limit values unit test conditions remarks min. typ. max. u1 input low voltage v il -0.2 0.4 v u2 input high voltage v ih v bat -0.4 v bat + 0.2 v u3 output low voltage v ol 0.5 v i ol =1.6ma targetdatasheet.book page 142 monday, april 28, 2008 11:16 am
preliminary data sheet 143 v0.9, 2008-04-28 PMA7110 reference u4 output high voltage v oh v bat -0.5 v i oh = -1.6ma u6 output transition time t thl , t tlh 30 ns 20pf load, 10% ... 90% u7 input capacitance c pad 2pf u8 internal pullup or pulldown resistor r uppx , r downppx 1) 35 50 65 kohm u9 internal pullup or pulldown resistor r upppy , r downppy 2) 175 250 325 kohm 1) ppx are: pp0, pp1, pp4, pp5, pp6, pp7 2) ppy are: pp2, pp3, pp8, pp9 # parameter symbol limit values unit test conditions remarks min. typ. max. targetdatasheet.book page 143 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 144 v0.9, 2008-04-28 3.2 reference sfr registers this section contains detailed description about sfrs which are shown in figure 7 "sfr special function register address overview" on page 53 but not described in chapter ?functional description . table 93 sfr address db h : adcc0- adc configuration register 0 table 94 sfr address dc h : adcc1- adc configuration register 1 table 95 sfr address d4 h : adccl- adc configuration register (low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. tvc2 tvc1 tvc0 n.u. stc2 stc1 stc0 0/0 rw 0/0 rw 0/0 rw 0/0 0/0 r/w 0/0 rw 0/0 rw 0/0 tcv2 internal clock divider bit 2 tcv1 internal clock divider bit 1 tcv0 internal clock divider bit 0 stc2 sample time adjustment bit 2 stc1 sample time adjustment bit 1 stc0 sample time adjustment bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sedc csi gain1 gain0 fcnsc subc2 subc1 subc0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 r/w 0/0 rw 0/0 rw 0/0 sedc single ended/differential conversion csi comparator signal inversion gain1 gain setting of the 10-bit c-network bit 1 gain0 gain setting of the 10-bit c-network bit 0 fcnsc full conversion or subconversion subc2 subconversion bit 2 subc1 subconversion bit 1 subc0 subconversion bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcd.7 adcd.6 adcd.5 adcd.4 adcd.3 adcd.2 adcd.1 adcd.0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 adcd.7 - adcd.0 bit 7 - bit 0 targetdatasheet.book page 144 monday, april 28, 2008 11:16 am
preliminary data sheet 145 v0.9, 2008-04-28 PMA7110 reference table 96 sfr address d5 h : adcch- adc configuration register (high byte) table 97 sfr address d2 h : adcm- adc mode register table 98 sfr address da h : adcoff- adc input offset c-network configuration bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. adcd.9 adcd.8 0/0 0/0 0/0 0/0 0/0 0/0 r 0/0 r 0/0 adcd.9 bit 9 adcd.8 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcstart rv2 rv1 rv0 wbcstart cs2 cs1 cs0 rcw 0/0 rw 1/1 rw 1/1 rw 1/1 rcw 0/0 rw 1/1 rw 1/1 rw 1/1 adcstart adc conversion start rv2 reference voltage select bit 2 rv1 reference voltage select bit 1 rv0 reference voltage select bit 0 wbcstart wbc start cs2 analog channel select bit 2 cs1 analog channel select bit 1 cs0 analog channel select bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 off5 off5 off5 rv0 wbcstart cs2 cs1 cs0 r 0/0 r 0/0 rw 0/0 rw 1/1 rcw 0/0 rw 1/1 rw 1/1 rw 1/1 off5 bit 5 (extended) off5 bit 5 (extended) off5 input of offset c-network bit 5 off4 input of offset c-network bit 4 off3 input of offset c-network bit 3 off2 input of offset c-network bit 2 off1 input of offset c-network bit 1 off0 input of offset c-network bit 0 targetdatasheet.book page 145 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 146 v0.9, 2008-04-28 table 99 sfr address d3 h : adcs- adc startus register table 100 sfr address dd h : adwbc- ad wbc wire bond check table 101 sfr address e9 h : fcsp- flash control register - sector protection control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. sarsatl sarsath cl000 cg3ff n.u. sample busy 0/0 r 0/0 r 0/0 r 0/0 r 0/0 0/0 r 0/0 r 0/0 sarsatl negative saturation of sar sarsath positive saturation of sar cl000 0x000 saturation of c-net control word cg3ff 0x3ff saturation of c-net control word sample sample/hold busy busy bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. stat3 stat2 dref wbef 0/0 0/0 0/0 0/0 r 0/0 r 0/0 r 0/0 r 0/0 stat3 reserved stat2 reserved dref diagnostic resistor error flag busy wire bond error flagl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eccerr eccleft eccoff wlo wle singlestep codelck conflck rc 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rmw u/0 rmw u/0 eccerr ecc error detected bit (0=no error, 1=error detected) eccleft ecc vector selection for read/write (0=select lower 8-bit, 1=selects left 4 bits) eccoff bypass ecc wlo selects all odd wordlines wle selects all even wordlines singlestep flash single-step mode codelck code-sector lock bit (0=programmable & erasable; 1=read only) conlck config-sector lock bit (0=programmable & erasable; 1=read only) targetdatasheet.book page 146 monday, april 28, 2008 11:16 am
preliminary data sheet 147 v0.9, 2008-04-28 PMA7110 reference table 102 sfr address ea h : fcs- flash control register - status model table 103 sfr address e1 h : fcpp0- flash charge pumps power control register 0l table 104 sfr address e2 h : fcpp1- flash charge pumps power control register 1l bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iprog ierase iread ipdw n prog erase read pdwn r 0/0 r 0/0 r 0/0 r 1/1 rw 0/0 rw 0/0 rw 0/0 rw 1/1 iprog indicates that the flash is in program mode ierase indicates that the flash is in erase mode iread indicates that the flash is in read mode ipdwn indicates that the flash is in powerdown mode prog program enable bit: 0->1: starts transition into program mode erase erase enable bit: 0->1: starts transition into erase mode read read enable bit: 0->1: starts transition into read mode pdwn cpdwn enable bit: 0->1: starts transition into powerdown mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vprogn1 vprogn0 vprognen vpp3 vpp2 vpp1 vpp0 vppen rw 0/0 rw 0/0 rw 0/0 rw0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 vprogn1 also used for ssdi<7> and disconcg vprogn0 also used for ssdi<6> vprognen also used for ssdi<5> vpp3 also used for ssdi<4> and dmux <3> and longeval vpp2 also used for ssdi<3> and dmux <2> vpp1 also used for ssdi<2> and dmux <1> vpp0 also used for ssdi<1> and dmux <0> vppen also used for ssdi<0> bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vreadhi ibiashi vprogpbit4 vprogpbit3 vprogpbit2 vprogpbit1 vprogpbit0 vprogpen rw 0/0 rw 0/0 rw 0/0 rw0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 vreadhi increases cg-voltage from 1.8 v to 2.5 v during read ibiashi increases bias currents by 66% (from 5 ua to 8.33 ua) vprogpbit4 vprogpbit3 vprogpbit2 also used for ssdi<11> targetdatasheet.book page 147 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 148 v0.9, 2008-04-28 table 105 sfr address e3 h : fcserm- flash sector erase and read margin select registerl table 106 sfr address 84 h : mmr0 - memory mapped register 0 table 107 sfr address 85 h : mmr1 - memory mapped register 1 vprogpbit1 also used for ssdi<10> vprogpbit0 also used for ssdi<9> vprogpen also used for ssdi<8> bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usevext refcurmag1 refcurmag0 erselref erselconf ersels2 ersels1 ersels0 rw 0/0 rw 0/0 rw 1/1 rw0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 usevext uses voltage at vext to increase vprogp current refcur mag1 reference current magnitude, bit 1 refcur mag0 reference current magnitude, bit 0 erselr ef selects reference cells for erase erselc onf selects config-sector for erase ersels2 selects id-sector for erase ersels1 selects data-sector for erase ersels0 selects code-sector for erase bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 general / programming & debugging purposes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 general / programming & debugging purposes targetdatasheet.book page 148 monday, april 28, 2008 11:16 am
preliminary data sheet 149 v0.9, 2008-04-28 PMA7110 reference table 108 sfr address 86 h : mmr2 - memory mapped register 2 table 109 sfr address 81 h : sp - stack pointer table 110 sfr address 8c h : th0 - timer 0 register high byte table 111 sfr address 8d h : th1 - timer 1register high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 general / programming & debugging purposes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 0/0 0/0 0/0 0/0 0/0 rw 0/0 rw 0/0 rw 1/1 sp.7 -sp. 0 stackpointer bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 targetdatasheet.book page 149 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 150 v0.9, 2008-04-28 table 112 sfr address cd h : th2 - timer 2 register high byte table 113 sfr address cb h : th3 - timer 3register high byte table 114 sfr address 8a h : tl0 - timer 0 register low byte table 115 sfr address 8b h : tl1 - timer 1 register low byte table 116 sfr address cc h : tl2 - timer 2 register low byte table 117 sfr address ca h : tl3 - timer 3 register low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 - bit 0 bit 7 - bit 0 targetdatasheet.book page 150 monday, april 28, 2008 11:16 am
preliminary data sheet 151 v0.9, 2008-04-28 PMA7110 reference table 118 sfr address de h : rfvco -rf frequency synthesizer vco config table 119 sfr address d4 h : adcdl - adc result register (low byte) table 120 sfr address d5 h : adcdh - adc result register (high byte) table 121 sfr address aa h : crcd - crc data register table 122 sfr address ac h : crc0 - crc shift register(low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vcocc3 vcocc2 vcocc1 vcocc0 vcof3 vcof2 vcof1 vcof0 rw u/1 rw u/0 rw u/0 rw u/1 rw u/0 rw u/0 rw u/0 rw u/0 bit 7-4 vcocc3-0 vco core current select vcocc3 ... 1600a (msb) vcocc2 ... 800a vcocc1 ... 400a vcocc0 ... 200a (lsb) bit 3-0 vcof3-0 vco frequency range adjustment vco tuning curve select bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcd.7 adcd.6 adcd.5 adcd.4 adcd.3 adcd.2 adcd.1 adcd.0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 r 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. n.u. n.u. adcd.9 adcd.8 0/0 0/0 0/0 0/0 0/0 0/0 r 0/0 r 0/0 bit 1 adcd.9 bit 9 bit 0 adcd.8 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crcd.7 crcd.6 crcd.5 crcd.4 crcd.3 crcd.2 crcd.1 crcd.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crc.7 crc.6 crc.5 crc.4 crc.3 crc.2 crc.1 crc.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 targetdatasheet.book page 151 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 152 v0.9, 2008-04-28 table 123 sfr address ad h : crc1 - crc shift register(high byte) table 124 sfr address 94 h : dbcl0- cpu debug compare register 0 (low) table 125 sfr address 95 h : dbch0- cpu debug compare register 0 (high) table 126 sfr address 96 h : dbtl0- cpu debug target register 0 (low) table 127 sfr address 97 h : dbth0- cpu debug target register 0 (high) table 128 sfr address 9c h : dbcl1- cpu debug compare register 1 (low) table 129 sfr address 9d h : dbch1- cpu debug compare register 1 (high) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crc.15 crc.14 crc.13 crc.12 crc.11 crc.10 crc.9 crc.8 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcl.7 dbcl.6 dbcl.5 dbcl.4 dbcl.3 dbcl.2 dbcl.1 dbcl.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbch.7 dbch.6 dbch.5 dbch.4 dbch.3 dbch.2 dbch.1 dbch.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbtl.7 dbtl.6 dbtl.5 dbtl.4 dbtl.3 dbtl.2 dbtl.1 dbtl.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbth.7 dbth.6 dbth.5 dbth.4 dbth.3 dbth.2 dbth.1 dbth.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcl.7 dbcl.6 dbcl.5 dbcl.4 dbcl.3 dbcl.2 dbcl.1 dbcl.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 targetdatasheet.book page 152 monday, april 28, 2008 11:16 am
preliminary data sheet 153 v0.9, 2008-04-28 PMA7110 reference table 130 sfr address 9e h : dbtl1- cpu debug target register 1 (low) table 131 sfr address 9f h : dbth1- cpu debug target register 1 (high) table 132 sfr address e4 h : fctkas- flash tkill and analog output select register dbch.7 dbch.6 dbch.5 dbch.4 dbch.3 dbch.2 dbch.1 dbch.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbtl.7 dbtl.6 dbtl.5 dbtl.4 dbtl.3 dbtl.2 dbtl.1 dbtl.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbth.7 dbth.6 dbth.5 dbth.4 dbth.3 dbth.2 dbth.1 dbth.0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read0v9 clksel ansel3 ansel2 ansel1 ansel0 tkill1 tkill0 rw 0/0 rw 0/0 rw 1/1 rw 1/1 rw 1/1 rw 1/1 rw 1/1 rw 1/1 bit 7 read0v9 sets the read voltage to 0.9 v bit 6 clksel read clock select (0:g_clk, 1:memclk) bit 5 ansel3 analog output select, bit 3 bit 4 ansel2 analog output select, bit 2 bit 3 ansel1 analog output select, bit 1 bit 2 ansel0 analog output select, bit 0 bit 1 tkill1 tkill-time, bit 1 bit 0 tkill0 tkill-time, bit 0 targetdatasheet.book page 153 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 154 v0.9, 2008-04-28 table 133 sfr address e5 h : fcss- flash control register for single-step mode table 134 sfr address ef h : lbd- low battery detector control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 selrefcell1 selrefcell0 vppch vprogpch vprognch sscsb ssale sswrb rw 1/1 rw 1/1 r 0/0 r 0/0 r 0/0 rw 0/0 rw 0/0 rw 0/0 bit 7 selrefcell1 selects refcells#3 and #2 bit 6 selrefcell0 selects refcells#1 and #0 bit 5 vppch charge pump charging indicator for vpp bit 4 vprogpch charge pump charging indicator for vprogp bit 3 vprognch charge pump charging indicator for vprogn bit 2 sscsb single-step-chip-select-bar bit 1 ssale single-step-address-latch-enable bit 0 sswrb single-step-write-read-bar bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. n.u. n.u. lbd2v1 lbdf lbden lbdmen 0/0 0/0 0/0 0/0 rw 1/1 rc 0/0 rw 1/1 rw 1/1 bit 3 lbd2v1 low battery voltage switch (1?2.1v vext, 0?2.4v vddc) bit 2 lbdf low battery detector flag (1..supply voltage below threshold) bit 1 lbden low battery detector enable bit 0 lbdmen low battery detector measurement enable targetdatasheet.book page 154 monday, april 28, 2008 11:16 am
preliminary data sheet 155 v0.9, 2008-04-28 PMA7110 reference table 135 sfr address d6 h : oscconf- rc hf oscillator configuration register table 136 sfr address d7 h : rffspll- rf- frequency synthesizer pll configuration bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rneg2 rneg1 rneg0 rcoft4 rcoft3 rcoft2 rcoft1 rcoft0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 bit 7 rneg2 rneg setting of xtalosc (bit 2) bit 6 rneg1 rneg setting of xtalosc (bit 1) bit 5 rneg0 rneg setting of xtalosc (bit 0) bit 4 rcoft4 rc oscillator frequency tuning (bit 4) bit 3 rcoft3 rc oscillator frequency tuning (bit 3) bit 2 rcoft2 rc oscillator frequency tuning (bit 2) bit 1 rcoft1 rc oscillator frequency tuning (bit 1) bit 0 rcoft0 rc oscillator frequency tuning (bit 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fpdpol ddcc ablp1 ablp0 dcc1 dcc0 cpcu1 cpcu0 w 1/1 0/0 w 0/0 w 0/0 0/0 0/0 w 1/1 w 0/0 bit 7 fpdpol frequency-phase-detector polarity - must be '1' bit 6 ddcc disable rf divider duty cycle control bit 5 ablp1 antibacklash pulse width select (bit 1) bit 4 ablp0 antibacklash pulse width select (bit 0) bit 3 dcc1 rf divider duty cycle control (bit 1) bit 2 dcc0 rf divider duty cycle control (bit 0) bit 1 cpcu1 charge pump current select (bit 1) bit 0 cpcu0 charge pump current select (bit 0) targetdatasheet.book page 155 monday, april 28, 2008 11:16 am
PMA7110 reference preliminary data sheet 156 v0.9, 2008-04-28 table 137 sfr address de h : rfvco- rf- frequency synthesizer vco configuration table 138 sfr address df h : rffsld- rf- frequency synthesizer lock detector configuration table 139 sfr address bd h : tmax - tmax detector control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vcocc3 vcocc2 vcocc1 vcocc0 vcof3 vcof2 vcof1 vcof0 rw u/1 rw u/0 rw u/0 rw u/1 rw u/0 rw u/0 rw u/0 rw u/0 bit 7 - bit 0 vcocc3 - vcocc0 vco core current select (bit 3 - bit 0) bit 6 vcocc2 vco core current select (bit 2) bit 5 vcocc1 vco core current select (bit 1) bit 4 vcocc0 vco core current select (bit 0) bit 3 vcof3 vco tuning curve select (bit 3 - bit 0) bit 2 vcof2 vco tuning curve select (bit 2) bit 1 vcof1 vco tuning curve select (bit 1) bit 0 vcof0 vco tuning curve select (bit 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.u. n.u. nolock enlockdet ll3 ll2 ll1 ll0 0/0 0/0 rc 0/0 w u/0 w u/1 w u/0 w u/0 w u/0 bit 5 nolock pll lock indicator bit 4 enlockdet enable lock detector bit 3 - bit 0 ll3 -ll0 lock limit select (bit 3 - bit 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pd_tmax n.u. tmtr5 tmtr4 tmtr3 tmtr2 tmtr1 tmtr0 rw u/1 0/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 rw u/0 bit 7 pd_tmax power down tmax detector in run state if set. please note, tmax detector is always active in thermal shutdown state bit 5 - bit 0 tmtr5 - tmtr0 tmax detector shut down trigger/release tempr.trimming (lsb~1c nonlinear charcteristic) 000000b = min. temp. threshold (~90c) 111111b = max. temp. threshold (~135c) targetdatasheet.book page 156 monday, april 28, 2008 11:16 am
preliminary data sheet 157 v0.9, 2008-04-28 PMA7110 reference 3.3 reference documents this section contains documents used for cross- reference throughout this document. table 140 reference documents reference number document description [1] pma5110 rom library function guide targetdatasheet.book page 157 monday, april 28, 2008 11:16 am
PMA7110 package outlines preliminary data sheet 158 v0.9, 2008-04-28 4 package outlines figure 41 package outline p-tssop-38 table 141 order information type ordering code package PMA7110 tbd tssop38 you can find all of our packages, sorts of packing and others on our infineon internet page ?products?: http://www.infineon.com/products . targetdatasheet.book page 158 monday, april 28, 2008 11:16 am
www.infineon.com published by infineon technologies ag targetdatasheet.book page 159 monday, april 28, 2008 11:16 am

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